Microchip Technology Inc. ATSAME53J19A 2024.06.03 Microchip ATSAME53J19A Microcontroller CM4 r0p1 selectable true true 3 false 8 32 AC Analog Comparators AC 0x0 0x0 0x26 registers n AC 122 CALIB Calibration 0x24 16 read-write n 0x0 0x0 BIAS0 COMP0/1 Bias Scaling 0 2 COMPCTRL0 Comparator Control n 0x10 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0 HYST100 100mV 1 HYST150 150mV 2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 DAC DAC output 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect HIGH High speed 3 SWAP Swap Inputs and Invert 15 1 COMPCTRL1 Comparator Control n 0x14 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0 HYST100 100mV 1 HYST150 150mV 2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 DAC DAC output 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect HIGH High speed 3 SWAP Swap Inputs and Invert 15 1 COMPCTRL[0] Comparator Control n 0x20 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0 HYST100 100mV 1 HYST150 150mV 2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 DAC DAC output 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect HIGH High speed 3 SWAP Swap Inputs and Invert 15 1 COMPCTRL[1] Comparator Control n 0x34 32 read-write n 0x0 0x0 ENABLE Enable 1 1 FLEN Filter Length 24 3 FLENSelect OFF No filtering 0 MAJ3 3-bit majority function (2 of 3) 1 MAJ5 5-bit majority function (3 of 5) 2 HYST Hysteresis Level 20 2 HYSTSelect HYST50 50mV 0 HYST100 100mV 1 HYST150 150mV 2 HYSTEN Hysteresis Enable 19 1 INTSEL Interrupt Selection 3 2 INTSELSelect TOGGLE Interrupt on comparator output toggle 0 RISING Interrupt on comparator output rising 1 FALLING Interrupt on comparator output falling 2 EOC Interrupt on end of comparison (single-shot mode only) 3 MUXNEG Negative Input Mux Selection 8 3 MUXNEGSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 GND Ground 4 VSCALE VDD scaler 5 BANDGAP Internal bandgap voltage 6 DAC DAC output 7 MUXPOS Positive Input Mux Selection 12 3 MUXPOSSelect PIN0 I/O pin 0 0 PIN1 I/O pin 1 1 PIN2 I/O pin 2 2 PIN3 I/O pin 3 3 VSCALE VDD Scaler 4 OUT Output 28 2 OUTSelect OFF The output of COMPn is not routed to the COMPn I/O port 0 ASYNC The asynchronous output of COMPn is routed to the COMPn I/O port 1 SYNC The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port 2 RUNSTDBY Run in Standby 6 1 SINGLE Single-Shot Mode 2 1 SPEED Speed Selection 16 2 SPEEDSelect HIGH High speed 3 SWAP Swap Inputs and Invert 15 1 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 write-only n 0x0 0x0 START0 Comparator 0 Start Comparison 0 1 START1 Comparator 1 Start Comparison 1 1 DBGCTRL Debug Control 0x9 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x2 16 read-write n 0x0 0x0 COMPEI0 Comparator 0 Event Input Enable 8 1 COMPEI1 Comparator 1 Event Input Enable 9 1 COMPEO0 Comparator 0 Event Output Enable 0 1 COMPEO1 Comparator 1 Event Output Enable 1 1 INVEI0 Comparator 0 Input Event Invert Enable 12 1 INVEI1 Comparator 1 Input Event Invert Enable 13 1 WINEO0 Window 0 Event Output Enable 4 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 COMP0 Comparator 0 Interrupt Enable 0 1 COMP1 Comparator 1 Interrupt Enable 1 1 WIN0 Window 0 Interrupt Enable 4 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 COMP0 Comparator 0 0 1 COMP1 Comparator 1 1 1 WIN0 Window 0 4 1 SCALER0 Scaler n 0xC 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER1 Scaler n 0xD 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER[0] Scaler n 0x18 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 SCALER[1] Scaler n 0x25 8 read-write n 0x0 0x0 VALUE Scaler Value 0 6 STATUSA Status A 0x7 8 read-only n 0x0 0x0 STATE0 Comparator 0 Current State 0 1 STATE1 Comparator 1 Current State 1 1 WSTATE0 Window 0 Current State 4 2 WSTATE0Select ABOVE Signal is above window 0 INSIDE Signal is inside window 1 BELOW Signal is below window 2 STATUSB Status B 0x8 8 read-only n 0x0 0x0 READY0 Comparator 0 Ready 0 1 READY1 Comparator 1 Ready 1 1 SYNCBUSY Synchronization Busy 0x20 32 read-only n 0x0 0x0 COMPCTRL0 COMPCTRL 0 Synchronization Busy 3 1 COMPCTRL1 COMPCTRL 1 Synchronization Busy 4 1 ENABLE Enable Synchronization Busy 1 1 SWRST Software Reset Synchronization Busy 0 1 WINCTRL WINCTRL Synchronization Busy 2 1 WINCTRL Window Control 0xA 8 read-write n 0x0 0x0 WEN0 Window 0 Mode Enable 0 1 WINTSEL0 Window 0 Interrupt Selection 1 2 WINTSEL0Select ABOVE Interrupt on signal above window 0 INSIDE Interrupt on signal inside window 1 BELOW Interrupt on signal below window 2 OUTSIDE Interrupt on signal outside window 3 ADC0 Analog Digital Converter ADC 0x0 0x0 0x4A registers n ADC0_OTHER 118 ADC0_RESRDY 119 ADC_AVGCTRL Average Control 0xA 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0 2 2 samples 1 1024 1024 samples 10 4 4 samples 2 8 8 samples 3 16 16 samples 4 32 32 samples 5 64 64 samples 6 128 128 samples 7 256 256 samples 8 512 512 samples 9 ADC_CALIB Calibration 0x48 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASR2R Bias R2R Ampli scaling 4 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 ADC_CTRLA Control A 0x0 16 read-write n 0x0 0x0 DUALSEL Dual Mode Trigger Selection 3 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0 DIV4 Peripheral clock divided by 4 1 DIV8 Peripheral clock divided by 8 2 DIV16 Peripheral clock divided by 16 3 DIV32 Peripheral clock divided by 32 4 DIV64 Peripheral clock divided by 64 5 DIV128 Peripheral clock divided by 128 6 DIV256 Peripheral clock divided by 256 7 R2R Rail to Rail Operation Enable 15 1 RUNSTDBY Run in Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 ADC_CTRLB Control B 0x6 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 2 1 FREERUN Free Running Mode 1 1 LEFTADJ Left-Adjusted Result 0 1 RESSEL Conversion Result Resolution 3 2 RESSELSelect 12BIT 12-bit result 0 16BIT For averaging mode output 1 10BIT 10-bit result 2 8BIT 8-bit result 3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 WINSS Window Single Sample 11 1 ADC_DBGCTRL Debug Control 0x3 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 ADC_DSEQCTRL DMA Sequential Control 0x38 32 read-write n 0x0 0x0 AUTOSTART ADC Auto-Start Conversion 31 1 AVGCTRL Average Control 3 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 ADC_DSEQDATA DMA Sequencial Data 0x34 32 write-only n 0x0 0x0 DATA DMA Sequential Data 0 32 ADC_DSEQSTAT DMA Sequencial Status 0x3C 32 read-only n 0x0 0x0 AVGCTRL Average Control 3 1 BUSY DMA Sequencing Busy 31 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 ADC_EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Start Conversion Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 ADC_GAINCORR Gain Correction 0x10 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 ADC_INPUTCTRL Input Control 0x4 16 read-write n 0x0 0x0 DIFFMODE Differential Mode 7 1 DSEQSTOP Stop DMA Sequencing 15 1 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0 AIN1 ADC AIN1 Pin 1 AIN2 ADC AIN2 Pin 2 GND Internal Ground 24 AIN3 ADC AIN3 Pin 3 AIN4 ADC AIN4 Pin 4 AIN5 ADC AIN5 Pin 5 AIN6 ADC AIN6 Pin 6 AIN7 ADC AIN7 Pin 7 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0 AIN1 ADC AIN1 Pin 1 AIN10 ADC AIN10 Pin 10 AIN11 ADC AIN11 Pin 11 AIN12 ADC AIN12 Pin 12 AIN13 ADC AIN13 Pin 13 AIN14 ADC AIN14 Pin 14 AIN15 ADC AIN15 Pin 15 AIN16 ADC AIN16 Pin 16 AIN17 ADC AIN17 Pin 17 AIN18 ADC AIN18 Pin 18 AIN19 ADC AIN19 Pin 19 AIN2 ADC AIN2 Pin 2 AIN20 ADC AIN20 Pin 20 AIN21 ADC AIN21 Pin 21 AIN22 ADC AIN22 Pin 22 AIN23 ADC AIN23 Pin 23 SCALEDCOREVCC 1/4 Scaled Core Supply 24 SCALEDVBAT 1/4 Scaled VBAT Supply 25 SCALEDIOVCC 1/4 Scaled I/O Supply 26 BANDGAP Bandgap Voltage 27 PTAT Temperature Sensor 28 CTAT Temperature Sensor 29 AIN3 ADC AIN3 Pin 3 DAC DAC Output 30 PTC PTC output (only on ADC0) 31 AIN4 ADC AIN4 Pin 4 AIN5 ADC AIN5 Pin 5 AIN6 ADC AIN6 Pin 6 AIN7 ADC AIN7 Pin 7 AIN8 ADC AIN8 Pin 8 AIN9 ADC AIN9 Pin 9 ADC_INTENCLR Interrupt Enable Clear 0x2C 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 ADC_INTENSET Interrupt Enable Set 0x2D 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 ADC_INTFLAG Interrupt Flag Status and Clear 0x2E 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 ADC_OFFSETCORR Offset Correction 0x12 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 ADC_REFCTRL Reference Control 0x8 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0 INTVCC0 1/2 VDDANA 2 INTVCC1 VDDANA 3 AREFA External Reference 4 AREFB External Reference 5 AREFC External Reference (only on ADC1) 6 ADC_RESS Last Sample Result 0x44 16 read-only n 0x0 0x0 RESS Last ADC conversion result 0 16 ADC_RESULT Result Conversion Value 0x40 16 read-only n 0x0 0x0 RESULT Result Conversion Value 0 16 ADC_SAMPCTRL Sample Time Control 0xB 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 ADC_STATUS Status 0x2F 8 read-only n 0x0 0x0 ADCBUSY ADC Busy Status 0 1 WCC Window Comparator Counter 2 6 ADC_SWTRIG Software Trigger 0x14 8 read-write n 0x0 0x0 FLUSH ADC Conversion Flush 0 1 START Start ADC Conversion 1 1 ADC_SYNCBUSY Synchronization Busy 0x30 32 read-only n 0x0 0x0 AVGCTRL Average Control Synchronization Busy 5 1 CTRLB Control B Synchronization Busy 3 1 ENABLE ENABLE Synchronization Busy 1 1 GAINCORR Gain Correction Synchronization Busy 9 1 INPUTCTRL Input Control Synchronization Busy 2 1 OFFSETCORR Offset Correction Synchronization Busy 10 1 REFCTRL Reference Control Synchronization Busy 4 1 SAMPCTRL Sampling Time Control Synchronization Busy 6 1 SWRST SWRST Synchronization Busy 0 1 SWTRIG Software Trigger Synchronization Busy 11 1 WINLT Window Monitor Lower Threshold Synchronization Busy 7 1 WINUT Window Monitor Upper Threshold Synchronization Busy 8 1 ADC_WINLT Window Monitor Lower Threshold 0xC 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 ADC_WINUT Window Monitor Upper Threshold 0xE 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 AVGCTRL Average Control 0xA 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA CALIB Calibration 0x48 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASR2R Bias R2R Ampli scaling 4 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 CTRLA Control A 0x0 16 read-write n 0x0 0x0 DUALSEL Dual Mode Trigger Selection 3 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0 DIV4 Peripheral clock divided by 4 1 DIV8 Peripheral clock divided by 8 2 DIV16 Peripheral clock divided by 16 3 DIV32 Peripheral clock divided by 32 4 DIV64 Peripheral clock divided by 64 5 DIV128 Peripheral clock divided by 128 6 DIV256 Peripheral clock divided by 256 7 R2R Rail to Rail Operation Enable 15 1 RUNSTDBY Run in Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 CTRLB Control B 0x6 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 2 1 FREERUN Free Running Mode 1 1 LEFTADJ Left-Adjusted Result 0 1 RESSEL Conversion Result Resolution 3 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 WINSS Window Single Sample 11 1 DBGCTRL Debug Control 0x3 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 DSEQCTRL DMA Sequential Control 0x38 32 read-write n 0x0 0x0 AUTOSTART ADC Auto-Start Conversion 31 1 AVGCTRL Average Control 3 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 DSEQDATA DMA Sequencial Data 0x34 32 write-only n 0x0 0x0 DATA DMA Sequential Data 0 32 DSEQSTAT DMA Sequencial Status 0x3C 32 read-only n 0x0 0x0 AVGCTRL Average Control 3 1 BUSY DMA Sequencing Busy 31 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Start Conversion Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x10 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x4 16 read-write n 0x0 0x0 DIFFMODE Differential Mode 7 1 DSEQSTOP Stop DMA Sequencing 15 1 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 GND Internal Ground 0x18 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN16 ADC AIN16 Pin 0x10 AIN17 ADC AIN17 Pin 0x11 AIN18 ADC AIN18 Pin 0x12 AIN19 ADC AIN19 Pin 0x13 AIN20 ADC AIN20 Pin 0x14 AIN21 ADC AIN21 Pin 0x15 AIN22 ADC AIN22 Pin 0x16 AIN23 ADC AIN23 Pin 0x17 SCALEDCOREVCC 1/4 Scaled Core Supply 0x18 SCALEDVBAT 1/4 Scaled VBAT Supply 0x19 SCALEDIOVCC 1/4 Scaled I/O Supply 0x1A BANDGAP Bandgap Voltage 0x1B PTAT Temperature Sensor TSENSP 0x1C CTAT Temperature Sensor TSENSC 0x1D DAC DAC Output 0x1E PTC PTC output (only on ADC0) 0x1F AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB AIN12 ADC AIN12 Pin 0xC AIN13 ADC AIN13 Pin 0xD AIN14 ADC AIN14 Pin 0xE AIN15 ADC AIN15 Pin 0xF INTENCLR Interrupt Enable Clear 0x2C 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x2D 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x2E 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 OFFSETCORR Offset Correction 0x12 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x8 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/2 VDDANA 0x2 INTVCC1 VDDANA 0x3 AREFA External Reference A 0x4 AREFB External Reference B 0x5 AREFC External Reference C (only on ADC1) 0x6 RESS Last Sample Result 0x44 16 read-only n 0x0 0x0 RESS Last ADC conversion result 0 16 RESULT Result Conversion Value 0x40 16 read-only n 0x0 0x0 RESULT Result Conversion Value 0 16 SAMPCTRL Sample Time Control 0xB 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 STATUS Status 0x2F 8 read-only n 0x0 0x0 ADCBUSY ADC Busy Status 0 1 WCC Window Comparator Counter 2 6 SWTRIG Software Trigger 0x14 8 read-write n 0x0 0x0 FLUSH ADC Conversion Flush 0 1 START Start ADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x30 32 read-only n 0x0 0x0 AVGCTRL Average Control Synchronization Busy 5 1 CTRLB Control B Synchronization Busy 3 1 ENABLE ENABLE Synchronization Busy 1 1 GAINCORR Gain Correction Synchronization Busy 9 1 INPUTCTRL Input Control Synchronization Busy 2 1 OFFSETCORR Offset Correction Synchronization Busy 10 1 REFCTRL Reference Control Synchronization Busy 4 1 SAMPCTRL Sampling Time Control Synchronization Busy 6 1 SWRST SWRST Synchronization Busy 0 1 SWTRIG Software Trigger Synchronization Busy 11 1 WINLT Window Monitor Lower Threshold Synchronization Busy 7 1 WINUT Window Monitor Upper Threshold Synchronization Busy 8 1 WINLT Window Monitor Lower Threshold 0xC 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0xE 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 ADC1 Analog Digital Converter ADC 0x0 0x0 0x4A registers n ADC1_OTHER 120 ADC1_RESRDY 121 ADC_AVGCTRL Average Control 0xA 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0 2 2 samples 1 1024 1024 samples 10 4 4 samples 2 8 8 samples 3 16 16 samples 4 32 32 samples 5 64 64 samples 6 128 128 samples 7 256 256 samples 8 512 512 samples 9 ADC_CALIB Calibration 0x48 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASR2R Bias R2R Ampli scaling 4 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 ADC_CTRLA Control A 0x0 16 read-write n 0x0 0x0 DUALSEL Dual Mode Trigger Selection 3 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0 DIV4 Peripheral clock divided by 4 1 DIV8 Peripheral clock divided by 8 2 DIV16 Peripheral clock divided by 16 3 DIV32 Peripheral clock divided by 32 4 DIV64 Peripheral clock divided by 64 5 DIV128 Peripheral clock divided by 128 6 DIV256 Peripheral clock divided by 256 7 R2R Rail to Rail Operation Enable 15 1 RUNSTDBY Run in Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 ADC_CTRLB Control B 0x6 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 2 1 FREERUN Free Running Mode 1 1 LEFTADJ Left-Adjusted Result 0 1 RESSEL Conversion Result Resolution 3 2 RESSELSelect 12BIT 12-bit result 0 16BIT For averaging mode output 1 10BIT 10-bit result 2 8BIT 8-bit result 3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 WINSS Window Single Sample 11 1 ADC_DBGCTRL Debug Control 0x3 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 ADC_DSEQCTRL DMA Sequential Control 0x38 32 read-write n 0x0 0x0 AUTOSTART ADC Auto-Start Conversion 31 1 AVGCTRL Average Control 3 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 ADC_DSEQDATA DMA Sequencial Data 0x34 32 write-only n 0x0 0x0 DATA DMA Sequential Data 0 32 ADC_DSEQSTAT DMA Sequencial Status 0x3C 32 read-only n 0x0 0x0 AVGCTRL Average Control 3 1 BUSY DMA Sequencing Busy 31 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 ADC_EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Start Conversion Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 ADC_GAINCORR Gain Correction 0x10 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 ADC_INPUTCTRL Input Control 0x4 16 read-write n 0x0 0x0 DIFFMODE Differential Mode 7 1 DSEQSTOP Stop DMA Sequencing 15 1 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0 AIN1 ADC AIN1 Pin 1 AIN2 ADC AIN2 Pin 2 GND Internal Ground 24 AIN3 ADC AIN3 Pin 3 AIN4 ADC AIN4 Pin 4 AIN5 ADC AIN5 Pin 5 AIN6 ADC AIN6 Pin 6 AIN7 ADC AIN7 Pin 7 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0 AIN1 ADC AIN1 Pin 1 AIN10 ADC AIN10 Pin 10 AIN11 ADC AIN11 Pin 11 AIN12 ADC AIN12 Pin 12 AIN13 ADC AIN13 Pin 13 AIN14 ADC AIN14 Pin 14 AIN15 ADC AIN15 Pin 15 AIN16 ADC AIN16 Pin 16 AIN17 ADC AIN17 Pin 17 AIN18 ADC AIN18 Pin 18 AIN19 ADC AIN19 Pin 19 AIN2 ADC AIN2 Pin 2 AIN20 ADC AIN20 Pin 20 AIN21 ADC AIN21 Pin 21 AIN22 ADC AIN22 Pin 22 AIN23 ADC AIN23 Pin 23 SCALEDCOREVCC 1/4 Scaled Core Supply 24 SCALEDVBAT 1/4 Scaled VBAT Supply 25 SCALEDIOVCC 1/4 Scaled I/O Supply 26 BANDGAP Bandgap Voltage 27 PTAT Temperature Sensor 28 CTAT Temperature Sensor 29 AIN3 ADC AIN3 Pin 3 DAC DAC Output 30 PTC PTC output (only on ADC0) 31 AIN4 ADC AIN4 Pin 4 AIN5 ADC AIN5 Pin 5 AIN6 ADC AIN6 Pin 6 AIN7 ADC AIN7 Pin 7 AIN8 ADC AIN8 Pin 8 AIN9 ADC AIN9 Pin 9 ADC_INTENCLR Interrupt Enable Clear 0x2C 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 ADC_INTENSET Interrupt Enable Set 0x2D 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 ADC_INTFLAG Interrupt Flag Status and Clear 0x2E 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 ADC_OFFSETCORR Offset Correction 0x12 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 ADC_REFCTRL Reference Control 0x8 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0 INTVCC0 1/2 VDDANA 2 INTVCC1 VDDANA 3 AREFA External Reference 4 AREFB External Reference 5 AREFC External Reference (only on ADC1) 6 ADC_RESS Last Sample Result 0x44 16 read-only n 0x0 0x0 RESS Last ADC conversion result 0 16 ADC_RESULT Result Conversion Value 0x40 16 read-only n 0x0 0x0 RESULT Result Conversion Value 0 16 ADC_SAMPCTRL Sample Time Control 0xB 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 ADC_STATUS Status 0x2F 8 read-only n 0x0 0x0 ADCBUSY ADC Busy Status 0 1 WCC Window Comparator Counter 2 6 ADC_SWTRIG Software Trigger 0x14 8 read-write n 0x0 0x0 FLUSH ADC Conversion Flush 0 1 START Start ADC Conversion 1 1 ADC_SYNCBUSY Synchronization Busy 0x30 32 read-only n 0x0 0x0 AVGCTRL Average Control Synchronization Busy 5 1 CTRLB Control B Synchronization Busy 3 1 ENABLE ENABLE Synchronization Busy 1 1 GAINCORR Gain Correction Synchronization Busy 9 1 INPUTCTRL Input Control Synchronization Busy 2 1 OFFSETCORR Offset Correction Synchronization Busy 10 1 REFCTRL Reference Control Synchronization Busy 4 1 SAMPCTRL Sampling Time Control Synchronization Busy 6 1 SWRST SWRST Synchronization Busy 0 1 SWTRIG Software Trigger Synchronization Busy 11 1 WINLT Window Monitor Lower Threshold Synchronization Busy 7 1 WINUT Window Monitor Upper Threshold Synchronization Busy 8 1 ADC_WINLT Window Monitor Lower Threshold 0xC 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 ADC_WINUT Window Monitor Upper Threshold 0xE 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 AVGCTRL Average Control 0xA 8 read-write n 0x0 0x0 ADJRES Adjusting Result / Division Coefficient 4 3 SAMPLENUM Number of Samples to be Collected 0 4 SAMPLENUMSelect 1 1 sample 0x0 2 2 samples 0x1 4 4 samples 0x2 8 8 samples 0x3 16 16 samples 0x4 32 32 samples 0x5 64 64 samples 0x6 128 128 samples 0x7 256 256 samples 0x8 512 512 samples 0x9 1024 1024 samples 0xA CALIB Calibration 0x48 16 read-write n 0x0 0x0 BIASCOMP Bias Comparator Scaling 0 3 BIASR2R Bias R2R Ampli scaling 4 3 BIASREFBUF Bias Reference Buffer Scaling 8 3 CTRLA Control A 0x0 16 read-write n 0x0 0x0 DUALSEL Dual Mode Trigger Selection 3 2 DUALSELSelect BOTH Start event or software trigger will start a conversion on both ADCs 0 INTERLEAVE START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 1 ENABLE Enable 1 1 ONDEMAND On Demand Control 7 1 PRESCALER Prescaler Configuration 8 3 PRESCALERSelect DIV2 Peripheral clock divided by 2 0 DIV4 Peripheral clock divided by 4 1 DIV8 Peripheral clock divided by 8 2 DIV16 Peripheral clock divided by 16 3 DIV32 Peripheral clock divided by 32 4 DIV64 Peripheral clock divided by 64 5 DIV128 Peripheral clock divided by 128 6 DIV256 Peripheral clock divided by 256 7 R2R Rail to Rail Operation Enable 15 1 RUNSTDBY Run in Standby 6 1 SLAVEEN Slave Enable 5 1 SWRST Software Reset 0 1 CTRLB Control B 0x6 16 read-write n 0x0 0x0 CORREN Digital Correction Logic Enable 2 1 FREERUN Free Running Mode 1 1 LEFTADJ Left-Adjusted Result 0 1 RESSEL Conversion Result Resolution 3 2 RESSELSelect 12BIT 12-bit result 0x0 16BIT For averaging mode output 0x1 10BIT 10-bit result 0x2 8BIT 8-bit result 0x3 WINMODE Window Monitor Mode 8 3 WINMODESelect DISABLE No window mode (default) 0 MODE1 RESULT > WINLT 1 MODE2 RESULT < WINUT 2 MODE3 WINLT < RESULT < WINUT 3 MODE4 !(WINLT < RESULT < WINUT) 4 WINSS Window Single Sample 11 1 DBGCTRL Debug Control 0x3 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 DSEQCTRL DMA Sequential Control 0x38 32 read-write n 0x0 0x0 AUTOSTART ADC Auto-Start Conversion 31 1 AVGCTRL Average Control 3 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 DSEQDATA DMA Sequencial Data 0x34 32 write-only n 0x0 0x0 DATA DMA Sequential Data 0 32 DSEQSTAT DMA Sequencial Status 0x3C 32 read-only n 0x0 0x0 AVGCTRL Average Control 3 1 BUSY DMA Sequencing Busy 31 1 CTRLB Control B 1 1 GAINCORR Gain Correction 7 1 INPUTCTRL Input Control 0 1 OFFSETCORR Offset Correction 8 1 REFCTRL Reference Control 2 1 SAMPCTRL Sampling Time Control 4 1 WINLT Window Monitor Lower Threshold 5 1 WINUT Window Monitor Upper Threshold 6 1 EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 FLUSHEI Flush Event Input Enable 0 1 FLUSHINV Flush Event Invert Enable 2 1 RESRDYEO Result Ready Event Out 4 1 STARTEI Start Conversion Event Input Enable 1 1 STARTINV Start Conversion Event Invert Enable 3 1 WINMONEO Window Monitor Event Out 5 1 GAINCORR Gain Correction 0x10 16 read-write n 0x0 0x0 GAINCORR Gain Correction Value 0 12 INPUTCTRL Input Control 0x4 16 read-write n 0x0 0x0 DIFFMODE Differential Mode 7 1 DSEQSTOP Stop DMA Sequencing 15 1 MUXNEG Negative Mux Input Selection 8 5 MUXNEGSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 GND Internal Ground 0x18 AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 MUXPOS Positive Mux Input Selection 0 5 MUXPOSSelect AIN0 ADC AIN0 Pin 0x0 AIN1 ADC AIN1 Pin 0x1 AIN16 ADC AIN16 Pin 0x10 AIN17 ADC AIN17 Pin 0x11 AIN18 ADC AIN18 Pin 0x12 AIN19 ADC AIN19 Pin 0x13 AIN20 ADC AIN20 Pin 0x14 AIN21 ADC AIN21 Pin 0x15 AIN22 ADC AIN22 Pin 0x16 AIN23 ADC AIN23 Pin 0x17 SCALEDCOREVCC 1/4 Scaled Core Supply 0x18 SCALEDVBAT 1/4 Scaled VBAT Supply 0x19 SCALEDIOVCC 1/4 Scaled I/O Supply 0x1A BANDGAP Bandgap Voltage 0x1B PTAT Temperature Sensor TSENSP 0x1C CTAT Temperature Sensor TSENSC 0x1D DAC DAC Output 0x1E PTC PTC output (only on ADC0) 0x1F AIN2 ADC AIN2 Pin 0x2 AIN3 ADC AIN3 Pin 0x3 AIN4 ADC AIN4 Pin 0x4 AIN5 ADC AIN5 Pin 0x5 AIN6 ADC AIN6 Pin 0x6 AIN7 ADC AIN7 Pin 0x7 AIN8 ADC AIN8 Pin 0x8 AIN9 ADC AIN9 Pin 0x9 AIN10 ADC AIN10 Pin 0xA AIN11 ADC AIN11 Pin 0xB AIN12 ADC AIN12 Pin 0xC AIN13 ADC AIN13 Pin 0xD AIN14 ADC AIN14 Pin 0xE AIN15 ADC AIN15 Pin 0xF INTENCLR Interrupt Enable Clear 0x2C 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Disable 1 1 RESRDY Result Ready Interrupt Disable 0 1 WINMON Window Monitor Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x2D 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Enable 1 1 RESRDY Result Ready Interrupt Enable 0 1 WINMON Window Monitor Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x2E 8 read-write n 0x0 0x0 OVERRUN Overrun Interrupt Flag 1 1 RESRDY Result Ready Interrupt Flag 0 1 WINMON Window Monitor Interrupt Flag 2 1 OFFSETCORR Offset Correction 0x12 16 read-write n 0x0 0x0 OFFSETCORR Offset Correction Value 0 12 REFCTRL Reference Control 0x8 8 read-write n 0x0 0x0 REFCOMP Reference Buffer Offset Compensation Enable 7 1 REFSEL Reference Selection 0 4 REFSELSelect INTREF Internal Bandgap Reference 0x0 INTVCC0 1/2 VDDANA 0x2 INTVCC1 VDDANA 0x3 AREFA External Reference A 0x4 AREFB External Reference B 0x5 AREFC External Reference C (only on ADC1) 0x6 RESS Last Sample Result 0x44 16 read-only n 0x0 0x0 RESS Last ADC conversion result 0 16 RESULT Result Conversion Value 0x40 16 read-only n 0x0 0x0 RESULT Result Conversion Value 0 16 SAMPCTRL Sample Time Control 0xB 8 read-write n 0x0 0x0 OFFCOMP Comparator Offset Compensation Enable 7 1 SAMPLEN Sampling Time Length 0 6 STATUS Status 0x2F 8 read-only n 0x0 0x0 ADCBUSY ADC Busy Status 0 1 WCC Window Comparator Counter 2 6 SWTRIG Software Trigger 0x14 8 read-write n 0x0 0x0 FLUSH ADC Conversion Flush 0 1 START Start ADC Conversion 1 1 SYNCBUSY Synchronization Busy 0x30 32 read-only n 0x0 0x0 AVGCTRL Average Control Synchronization Busy 5 1 CTRLB Control B Synchronization Busy 3 1 ENABLE ENABLE Synchronization Busy 1 1 GAINCORR Gain Correction Synchronization Busy 9 1 INPUTCTRL Input Control Synchronization Busy 2 1 OFFSETCORR Offset Correction Synchronization Busy 10 1 REFCTRL Reference Control Synchronization Busy 4 1 SAMPCTRL Sampling Time Control Synchronization Busy 6 1 SWRST SWRST Synchronization Busy 0 1 SWTRIG Software Trigger Synchronization Busy 11 1 WINLT Window Monitor Lower Threshold Synchronization Busy 7 1 WINUT Window Monitor Upper Threshold Synchronization Busy 8 1 WINLT Window Monitor Lower Threshold 0xC 16 read-write n 0x0 0x0 WINLT Window Lower Threshold 0 16 WINUT Window Monitor Upper Threshold 0xE 16 read-write n 0x0 0x0 WINUT Window Upper Threshold 0 16 AES Advanced Encryption Standard AES 0x0 0x0 0x88 registers n AES 130 CIPLEN Cipher Length 0x80 32 read-write n 0x0 0x0 CTRLA Control A 0x0 32 read-write n 0x0 0x0 AESMODE AES Modes of operation 2 3 AESMODESelect ECB Electronic code book mode 0 CBC Cipher block chaining mode 1 OFB Output feedback mode 2 CFB Cipher feedback mode 3 COUNTER Counter mode 4 CCM CCM mode 5 GCM Galois counter mode 6 CFBS Cipher Feedback Block Size 5 3 CFBSSelect 128BIT 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode 0 64BIT 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode 1 32BIT 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode 2 16BIT 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode 3 8BIT 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode 4 CIPHER Cipher Mode 10 1 CIPHERSelect DEC Decryption 0 ENC Encryption 1 CTYPE Counter Measure Type 16 4 ENABLE Enable 1 1 KEYGEN Last Key Generation 13 1 KEYGENSelect NONE No effect 0 LAST Start Computation of the last NK words of the expanded key 1 KEYSIZE Encryption Key Size 8 2 KEYSIZESelect 128BIT 128-bit Key for Encryption / Decryption 0 192BIT 192-bit Key for Encryption / Decryption 1 256BIT 256-bit Key for Encryption / Decryption 2 LOD Last Output Data Mode 12 1 LODSelect NONE No effect 0 LAST Start encryption in Last Output Data mode 1 STARTMODE Start Mode Select 11 1 STARTMODESelect MANUAL Start Encryption / Decryption in Manual mode 0 AUTO Start Encryption / Decryption in Auto mode 1 SWRST Software Reset 0 1 XORKEY XOR Key Operation 14 1 XORKEYSelect NONE No effect 0 XOR The user keyword gets XORed with the previous keyword register content. 1 CTRLB Control B 0x4 8 read-write n 0x0 0x0 EOM End of message 2 1 GFMUL GF Multiplication 3 1 NEWMSG New message 1 1 START Start Encryption/Decryption 0 1 DATABUFPTR Data buffer pointer 0x8 8 read-write n 0x0 0x0 INDATAPTR Input Data Pointer 0 2 DBGCTRL Debug control 0x9 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 GHASH0 Galois Hash n 0x6C 32 read-write n 0x0 0x0 GHASH1 Galois Hash n 0x70 32 read-write n 0x0 0x0 GHASH2 Galois Hash n 0x74 32 read-write n 0x0 0x0 GHASH3 Galois Hash n 0x78 32 read-write n 0x0 0x0 GHASH[0] Galois Hash n 0xD8 32 read-write n 0x0 0x0 GHASH[1] Galois Hash n 0x148 32 read-write n 0x0 0x0 GHASH[2] Galois Hash n 0x1BC 32 read-write n 0x0 0x0 GHASH[3] Galois Hash n 0x234 32 read-write n 0x0 0x0 HASHKEY0 Hash key n 0x5C 32 read-write n 0x0 0x0 HASHKEY1 Hash key n 0x60 32 read-write n 0x0 0x0 HASHKEY2 Hash key n 0x64 32 read-write n 0x0 0x0 HASHKEY3 Hash key n 0x68 32 read-write n 0x0 0x0 HASHKEY[0] Hash key n 0xB8 32 read-write n 0x0 0x0 HASHKEY[1] Hash key n 0x118 32 read-write n 0x0 0x0 HASHKEY[2] Hash key n 0x17C 32 read-write n 0x0 0x0 HASHKEY[3] Hash key n 0x1E4 32 read-write n 0x0 0x0 INDATA Indata 0x38 32 read-write n 0x0 0x0 INTENCLR Interrupt Enable Clear 0x5 8 read-write n 0x0 0x0 ENCCMP Encryption Complete Interrupt Enable 0 1 GFMCMP GF Multiplication Complete Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x6 8 read-write n 0x0 0x0 ENCCMP Encryption Complete Interrupt Enable 0 1 GFMCMP GF Multiplication Complete Interrupt Enable 1 1 INTFLAG Interrupt Flag Status 0x7 8 read-write n 0x0 0x0 ENCCMP Encryption Complete 0 1 GFMCMP GF Multiplication Complete 1 1 INTVECTV0 Initialisation Vector n 0x3C 32 write-only n 0x0 0x0 INTVECTV1 Initialisation Vector n 0x40 32 write-only n 0x0 0x0 INTVECTV2 Initialisation Vector n 0x44 32 write-only n 0x0 0x0 INTVECTV3 Initialisation Vector n 0x48 32 write-only n 0x0 0x0 INTVECTV[0] Initialisation Vector n 0x78 32 write-only n 0x0 0x0 INTVECTV[1] Initialisation Vector n 0xB8 32 write-only n 0x0 0x0 INTVECTV[2] Initialisation Vector n 0xFC 32 write-only n 0x0 0x0 INTVECTV[3] Initialisation Vector n 0x144 32 write-only n 0x0 0x0 KEYWORD0 Keyword n 0xC 32 write-only n 0x0 0x0 KEYWORD1 Keyword n 0x10 32 write-only n 0x0 0x0 KEYWORD2 Keyword n 0x14 32 write-only n 0x0 0x0 KEYWORD3 Keyword n 0x18 32 write-only n 0x0 0x0 KEYWORD4 Keyword n 0x1C 32 write-only n 0x0 0x0 KEYWORD5 Keyword n 0x20 32 write-only n 0x0 0x0 KEYWORD6 Keyword n 0x24 32 write-only n 0x0 0x0 KEYWORD7 Keyword n 0x28 32 write-only n 0x0 0x0 KEYWORD[0] Keyword n 0x18 32 write-only n 0x0 0x0 KEYWORD[1] Keyword n 0x28 32 write-only n 0x0 0x0 KEYWORD[2] Keyword n 0x3C 32 write-only n 0x0 0x0 KEYWORD[3] Keyword n 0x54 32 write-only n 0x0 0x0 KEYWORD[4] Keyword n 0x70 32 write-only n 0x0 0x0 KEYWORD[5] Keyword n 0x90 32 write-only n 0x0 0x0 KEYWORD[6] Keyword n 0xB4 32 write-only n 0x0 0x0 KEYWORD[7] Keyword n 0xDC 32 write-only n 0x0 0x0 RANDSEED Random Seed 0x84 32 read-write n 0x0 0x0 CCL Configurable Custom Logic CCL 0x0 0x0 0x18 registers n CTRL Control 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 SWRST Software Reset 0 1 LUTCTRL0 LUT Control x 0x8 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 EDGESELSelect DISABLE Edge detector is disabled 0 ENABLE Edge detector is enabled 1 ENABLE LUT Enable 1 1 ENABLESelect DISABLE LUT block is disabled 0 ENABLE LUT block is enabled 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 INVEISelect DISABLE Incoming event is not inverted 0 ENABLE Incoming event is inverted 1 LUTEI LUT Event Input Enable 21 1 LUTEISelect DISABLE LUT incoming event is disabled 0 ENABLE LUT incoming event is enabled 1 LUTEO LUT Event Output Enable 22 1 LUTEOSelect DISABLE LUT event output is disabled 0 ENABLE LUT event output is enabled 1 TRUTH Truth Value 24 8 LUTCTRL1 LUT Control x 0xC 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 EDGESELSelect DISABLE Edge detector is disabled 0 ENABLE Edge detector is enabled 1 ENABLE LUT Enable 1 1 ENABLESelect DISABLE LUT block is disabled 0 ENABLE LUT block is enabled 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 INVEISelect DISABLE Incoming event is not inverted 0 ENABLE Incoming event is inverted 1 LUTEI LUT Event Input Enable 21 1 LUTEISelect DISABLE LUT incoming event is disabled 0 ENABLE LUT incoming event is enabled 1 LUTEO LUT Event Output Enable 22 1 LUTEOSelect DISABLE LUT event output is disabled 0 ENABLE LUT event output is enabled 1 TRUTH Truth Value 24 8 LUTCTRL2 LUT Control x 0x10 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 EDGESELSelect DISABLE Edge detector is disabled 0 ENABLE Edge detector is enabled 1 ENABLE LUT Enable 1 1 ENABLESelect DISABLE LUT block is disabled 0 ENABLE LUT block is enabled 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 INVEISelect DISABLE Incoming event is not inverted 0 ENABLE Incoming event is inverted 1 LUTEI LUT Event Input Enable 21 1 LUTEISelect DISABLE LUT incoming event is disabled 0 ENABLE LUT incoming event is enabled 1 LUTEO LUT Event Output Enable 22 1 LUTEOSelect DISABLE LUT event output is disabled 0 ENABLE LUT event output is enabled 1 TRUTH Truth Value 24 8 LUTCTRL3 LUT Control x 0x14 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 EDGESELSelect DISABLE Edge detector is disabled 0 ENABLE Edge detector is enabled 1 ENABLE LUT Enable 1 1 ENABLESelect DISABLE LUT block is disabled 0 ENABLE LUT block is enabled 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 INVEISelect DISABLE Incoming event is not inverted 0 ENABLE Incoming event is inverted 1 LUTEI LUT Event Input Enable 21 1 LUTEISelect DISABLE LUT incoming event is disabled 0 ENABLE LUT incoming event is enabled 1 LUTEO LUT Event Output Enable 22 1 LUTEOSelect DISABLE LUT event output is disabled 0 ENABLE LUT event output is enabled 1 TRUTH Truth Value 24 8 LUTCTRL[0] LUT Control x 0x10 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 LUTEI LUT Event Input Enable 21 1 LUTEO LUT Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL[1] LUT Control x 0x1C 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 LUTEI LUT Event Input Enable 21 1 LUTEO LUT Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL[2] LUT Control x 0x2C 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 LUTEI LUT Event Input Enable 21 1 LUTEO LUT Event Output Enable 22 1 TRUTH Truth Value 24 8 LUTCTRL[3] LUT Control x 0x40 32 read-write n 0x0 0x0 EDGESEL Edge Selection 7 1 ENABLE LUT Enable 1 1 FILTSEL Filter Selection 4 2 FILTSELSelect DISABLE Filter disabled 0 SYNCH Synchronizer enabled 1 FILTER Filter enabled 2 INSEL0 Input Selection 0 8 4 INSEL0Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL1 Input Selection 1 12 4 INSEL1Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INSEL2 Input Selection 2 16 4 INSEL2Select MASK Masked input 0 FEEDBACK Feedback input source 1 LINK Linked LUT input source 2 EVENT Event input source 3 IO I/O pin input source 4 AC AC input source 5 TC TC input source 6 ALTTC Alternate TC input source 7 TCC TCC input source 8 SERCOM SERCOM input source 9 INVEI Inverted Event Input Enable 20 1 LUTEI LUT Event Input Enable 21 1 LUTEO LUT Event Output Enable 22 1 TRUTH Truth Value 24 8 SEQCTRL0 SEQ Control x 0x4 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 SEQCTRL1 SEQ Control x 0x5 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 SEQCTRL[0] SEQ Control x 0x8 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 SEQCTRL[1] SEQ Control x 0xD 8 read-write n 0x0 0x0 SEQSEL Sequential Selection 0 4 SEQSELSelect DISABLE Sequential logic is disabled 0 DFF D flip flop 1 JK JK flip flop 2 LATCH D latch 3 RS RS latch 4 CMCC Cortex M Cache Controller CMCC 0x0 0x0 0x38 registers n CFG Cache Configuration Register 0x4 32 read-write n 0x0 0x0 CSIZESW Cache size configured by software 4 3 CSIZESWSelect CONF_CSIZE_1KB The Cache Size is configured to 1KB 0 CONF_CSIZE_2KB The Cache Size is configured to 2KB 1 CONF_CSIZE_4KB The Cache Size is configured to 4KB 2 CONF_CSIZE_8KB The Cache Size is configured to 8KB 3 CONF_CSIZE_16KB The Cache Size is configured to 16KB 4 CONF_CSIZE_32KB The Cache Size is configured to 32KB 5 CONF_CSIZE_64KB The Cache Size is configured to 64KB 6 DCDIS Data Cache Disable 2 1 ICDIS Instruction Cache Disable 1 1 CTRL Cache Control Register 0x8 32 write-only n 0x0 0x0 CEN Cache Controller Enable 0 1 LCKWAY Cache Lock per Way Register 0x10 32 read-write n 0x0 0x0 LCKWAY Lockdown way Register 0 4 MAINT0 Cache Maintenance Register 0 0x20 32 write-only n 0x0 0x0 INVALL Cache Controller invalidate All 0 1 MAINT1 Cache Maintenance Register 1 0x24 32 write-only n 0x0 0x0 INDEX Invalidate Index 4 8 WAY Invalidate Way 28 4 WAYSelect WAY0 Way 0 is selection for index invalidation 0 WAY1 Way 1 is selection for index invalidation 1 WAY2 Way 2 is selection for index invalidation 2 WAY3 Way 3 is selection for index invalidation 3 MCFG Cache Monitor Configuration Register 0x28 32 read-write n 0x0 0x0 MODE Cache Controller Monitor Counter Mode 0 2 MODESelect CYCLE_COUNT Cycle counter 0 IHIT_COUNT Instruction hit counter 1 DHIT_COUNT Data hit counter 2 MCTRL Cache Monitor Control Register 0x30 32 write-only n 0x0 0x0 SWRST Cache Controller Software Reset 0 1 MEN Cache Monitor Enable Register 0x2C 32 read-write n 0x0 0x0 MENABLE Cache Controller Monitor Enable 0 1 MSR Cache Monitor Status Register 0x34 32 read-only n 0x0 0x0 EVENT_CNT Monitor Event Counter 0 32 SR Cache Status Register 0xC 32 read-only n 0x0 0x0 CSTS Cache Controller Status 0 1 TYPE Cache Type Register 0x0 32 read-only n 0x0 0x0 CLSIZE Cache Line Size 11 3 CLSIZESelect CLSIZE_4B Cache Line Size is 4 bytes 0 CLSIZE_8B Cache Line Size is 8 bytes 1 CLSIZE_16B Cache Line Size is 16 bytes 2 CLSIZE_32B Cache Line Size is 32 bytes 3 CLSIZE_64B Cache Line Size is 64 bytes 4 CLSIZE_128B Cache Line Size is 128 bytes 5 CSIZE Cache Size 8 3 CSIZESelect CSIZE_1KB Cache Size is 1 KB 0 CSIZE_2KB Cache Size is 2 KB 1 CSIZE_4KB Cache Size is 4 KB 2 CSIZE_8KB Cache Size is 8 KB 3 CSIZE_16KB Cache Size is 16 KB 4 CSIZE_32KB Cache Size is 32 KB 5 CSIZE_64KB Cache Size is 64 KB 6 GCLK dynamic Clock Gating supported 1 1 LCKDOWN Lock Down supported 7 1 RRP Round Robin Policy supported 4 1 WAYNUM Number of Way 5 2 WAYNUMSelect DMAPPED Direct Mapped Cache 0 ARCH2WAY 2-WAY set associative 1 ARCH4WAY 4-WAY set associative 2 CoreDebug Core Debug Register CoreDebug 0x0 0x0 0x10 registers n DCRDR Debug Core Register Data Register 0x8 32 read-write n 0x0 0x0 DCRSR Debug Core Register Selector Register 0x4 32 write-only n 0x0 0x0 REGSEL 0 5 REGWnR 16 1 DEMCR Debug Exception and Monitor Control Register 0xC 32 read-write n 0x0 0x0 MON_EN 16 1 MON_PEND 17 1 MON_REQ 19 1 MON_STEP 18 1 TRCENA 24 1 VC_BUSERR 8 1 VC_CHKERR 6 1 VC_CORERESET 0 1 VC_HARDERR 10 1 VC_INTERR 9 1 VC_MMERR 4 1 VC_NOCPERR 5 1 VC_STATERR 7 1 DHCSR Debug Halting Control and Status Register 0x0 32 read-write n 0x0 0x0 C_DEBUGEN 0 1 C_HALT 1 1 C_MASKINTS 3 1 C_SNAPSTALL 5 1 C_STEP 2 1 DBGKEY 16 16 write-only S_HALT 17 1 read-only S_LOCKUP 19 1 read-only S_REGRDY 16 1 read-only S_RESET_ST 25 1 read-only S_RETIRE_ST 24 1 read-only S_SLEEP 18 1 read-only DAC Digital-to-Analog Converter DAC 0x0 0x0 0x20 registers n DAC_OTHER 123 DAC_EMPTY_0 124 DAC_EMPTY_1 125 DAC_RESRDY_0 126 DAC_RESRDY_1 127 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable DAC Controller 1 1 SWRST Software Reset 0 1 CTRLB Control B 0x1 8 read-write n 0x0 0x0 DIFF Differential mode enable 0 1 REFSEL Reference Selection for DAC0/1 1 2 REFSELSelect VREFPU External reference unbuffered 0 VDDANA Analog supply 1 VREFPB External reference buffered 2 INTREF Internal bandgap reference 3 DACCTRL0 DAC n Control 0xC 16 read-write n 0x0 0x0 CCTRL Current Control 2 2 CCTRLSelect CC100K 100kSPS 0x0 CC1M 500kSPS 0x1 CC12M 1MSPS 0x2 DITHER Dithering Mode 7 1 ENABLE Enable DAC0 1 1 FEXT Standalone Filter 5 1 LEFTADJ Left Adjusted Data 0 1 OSR Sampling Rate 13 3 OSRSelect OSR_1 No Over Sampling 0 OSR_2 2x Over Sampling Ratio 1 OSR_4 4x Over Sampling Ratio 2 OSR_8 8x Over Sampling Ratio 3 OSR_16 16x Over Sampling Ratio 4 OSR_32 32x Over Sampling Ratio 5 REFRESH Refresh period 8 4 REFRESHSelect REFRESH_0 Do not Refresh 0 REFRESH_1 Refresh every 30 us 1 REFRESH_10 Refresh every 300 us 10 REFRESH_11 Refresh every 330 us 11 REFRESH_12 Refresh every 360 us 12 REFRESH_13 Refresh every 390 us 13 REFRESH_14 Refresh every 420 us 14 REFRESH_15 Refresh every 450 us 15 REFRESH_2 Refresh every 60 us 2 REFRESH_3 Refresh every 90 us 3 REFRESH_4 Refresh every 120 us 4 REFRESH_5 Refresh every 150 us 5 REFRESH_6 Refresh every 180 us 6 REFRESH_7 Refresh every 210 us 7 REFRESH_8 Refresh every 240 us 8 REFRESH_9 Refresh every 270 us 9 RUNSTDBY Run in Standby 6 1 DACCTRL1 DAC n Control 0xE 16 read-write n 0x0 0x0 CCTRL Current Control 2 2 CCTRLSelect CC100K 100kSPS 0x0 CC1M 500kSPS 0x1 CC12M 1MSPS 0x2 DITHER Dithering Mode 7 1 ENABLE Enable DAC0 1 1 FEXT Standalone Filter 5 1 LEFTADJ Left Adjusted Data 0 1 OSR Sampling Rate 13 3 OSRSelect OSR_1 No Over Sampling 0 OSR_2 2x Over Sampling Ratio 1 OSR_4 4x Over Sampling Ratio 2 OSR_8 8x Over Sampling Ratio 3 OSR_16 16x Over Sampling Ratio 4 OSR_32 32x Over Sampling Ratio 5 REFRESH Refresh period 8 4 REFRESHSelect REFRESH_0 Do not Refresh 0 REFRESH_1 Refresh every 30 us 1 REFRESH_10 Refresh every 300 us 10 REFRESH_11 Refresh every 330 us 11 REFRESH_12 Refresh every 360 us 12 REFRESH_13 Refresh every 390 us 13 REFRESH_14 Refresh every 420 us 14 REFRESH_15 Refresh every 450 us 15 REFRESH_2 Refresh every 60 us 2 REFRESH_3 Refresh every 90 us 3 REFRESH_4 Refresh every 120 us 4 REFRESH_5 Refresh every 150 us 5 REFRESH_6 Refresh every 180 us 6 REFRESH_7 Refresh every 210 us 7 REFRESH_8 Refresh every 240 us 8 REFRESH_9 Refresh every 270 us 9 RUNSTDBY Run in Standby 6 1 DACCTRL[0] DAC n Control 0x18 16 read-write n 0x0 0x0 CCTRL Current Control 2 2 CCTRLSelect CC100K 100kSPS 0 CC1M 500kSPS 1 CC12M 1MSPS 2 DITHER Dithering Mode 7 1 ENABLE Enable DAC0 1 1 FEXT Standalone Filter 5 1 LEFTADJ Left Adjusted Data 0 1 OSR Sampling Rate 13 3 OSRSelect OSR_1 No Over Sampling 0 OSR_2 2x Over Sampling Ratio 1 OSR_4 4x Over Sampling Ratio 2 OSR_8 8x Over Sampling Ratio 3 OSR_16 16x Over Sampling Ratio 4 OSR_32 32x Over Sampling Ratio 5 REFRESH Refresh period 8 4 REFRESHSelect REFRESH_0 Do not Refresh 0 REFRESH_1 Refresh every 30 us 1 REFRESH_10 Refresh every 300 us 10 REFRESH_11 Refresh every 330 us 11 REFRESH_12 Refresh every 360 us 12 REFRESH_13 Refresh every 390 us 13 REFRESH_14 Refresh every 420 us 14 REFRESH_15 Refresh every 450 us 15 REFRESH_2 Refresh every 60 us 2 REFRESH_3 Refresh every 90 us 3 REFRESH_4 Refresh every 120 us 4 REFRESH_5 Refresh every 150 us 5 REFRESH_6 Refresh every 180 us 6 REFRESH_7 Refresh every 210 us 7 REFRESH_8 Refresh every 240 us 8 REFRESH_9 Refresh every 270 us 9 RUNSTDBY Run in Standby 6 1 DACCTRL[1] DAC n Control 0x26 16 read-write n 0x0 0x0 CCTRL Current Control 2 2 CCTRLSelect CC100K 100kSPS 0 CC1M 500kSPS 1 CC12M 1MSPS 2 DITHER Dithering Mode 7 1 ENABLE Enable DAC0 1 1 FEXT Standalone Filter 5 1 LEFTADJ Left Adjusted Data 0 1 OSR Sampling Rate 13 3 OSRSelect OSR_1 No Over Sampling 0 OSR_2 2x Over Sampling Ratio 1 OSR_4 4x Over Sampling Ratio 2 OSR_8 8x Over Sampling Ratio 3 OSR_16 16x Over Sampling Ratio 4 OSR_32 32x Over Sampling Ratio 5 REFRESH Refresh period 8 4 REFRESHSelect REFRESH_0 Do not Refresh 0 REFRESH_1 Refresh every 30 us 1 REFRESH_10 Refresh every 300 us 10 REFRESH_11 Refresh every 330 us 11 REFRESH_12 Refresh every 360 us 12 REFRESH_13 Refresh every 390 us 13 REFRESH_14 Refresh every 420 us 14 REFRESH_15 Refresh every 450 us 15 REFRESH_2 Refresh every 60 us 2 REFRESH_3 Refresh every 90 us 3 REFRESH_4 Refresh every 120 us 4 REFRESH_5 Refresh every 150 us 5 REFRESH_6 Refresh every 180 us 6 REFRESH_7 Refresh every 210 us 7 REFRESH_8 Refresh every 240 us 8 REFRESH_9 Refresh every 270 us 9 RUNSTDBY Run in Standby 6 1 DATA0 DAC n Data 0x10 16 write-only n 0x0 0x0 DATA DAC0 Data 0 16 DATA1 DAC n Data 0x12 16 write-only n 0x0 0x0 DATA DAC0 Data 0 16 DATABUF0 DAC n Data Buffer 0x14 16 write-only n 0x0 0x0 DATABUF DAC0 Data Buffer 0 16 DATABUF1 DAC n Data Buffer 0x16 16 write-only n 0x0 0x0 DATABUF DAC0 Data Buffer 0 16 DATABUF[0] DAC n Data Buffer 0x28 16 write-only n 0x0 0x0 DATABUF DAC0 Data Buffer 0 16 DATABUF[1] DAC n Data Buffer 0x3E 16 write-only n 0x0 0x0 DATABUF DAC0 Data Buffer 0 16 DATA[0] DAC n Data 0x20 16 write-only n 0x0 0x0 DATA DAC0 Data 0 16 DATA[1] DAC n Data 0x32 16 write-only n 0x0 0x0 DATA DAC0 Data 0 16 DBGCTRL Debug Control 0x18 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 EVCTRL Event Control 0x2 8 read-write n 0x0 0x0 EMPTYEO0 Data Buffer Empty Event Output DAC 0 2 1 EMPTYEO1 Data Buffer Empty Event Output DAC 1 3 1 INVEI0 Enable Invertion of DAC 0 input event 4 1 INVEI1 Enable Invertion of DAC 1 input event 5 1 RESRDYEO0 Result Ready Event Output 0 6 1 RESRDYEO1 Result Ready Event Output 1 7 1 STARTEI0 Start Conversion Event Input DAC 0 0 1 STARTEI1 Start Conversion Event Input DAC 1 1 1 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 OVERRUN0 Overrun 0 Interrupt Enable 6 1 OVERRUN1 Overrun 1 Interrupt Enable 7 1 RESRDY0 Result 0 Ready Interrupt Enable 4 1 RESRDY1 Result 1 Ready Interrupt Enable 5 1 UNDERRUN0 Underrun 0 Interrupt Enable 0 1 UNDERRUN1 Underrun 1 Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EMPTY0 Data Buffer 0 Empty Interrupt Enable 2 1 EMPTY1 Data Buffer 1 Empty Interrupt Enable 3 1 OVERRUN0 Overrun 0 Interrupt Enable 6 1 OVERRUN1 Overrun 1 Interrupt Enable 7 1 RESRDY0 Result 0 Ready Interrupt Enable 4 1 RESRDY1 Result 1 Ready Interrupt Enable 5 1 UNDERRUN0 Underrun 0 Interrupt Enable 0 1 UNDERRUN1 Underrun 1 Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EMPTY0 Data Buffer 0 Empty 2 1 EMPTY1 Data Buffer 1 Empty 3 1 OVERRUN0 Result 0 Overrun 6 1 OVERRUN1 Result 1 Overrun 7 1 RESRDY0 Result 0 Ready 4 1 RESRDY1 Result 1 Ready 5 1 UNDERRUN0 Result 0 Underrun 0 1 UNDERRUN1 Result 1 Underrun 1 1 RESULT0 Filter Result 0x1C 16 read-only n 0x0 0x0 RESULT Filter Result 0 16 RESULT1 Filter Result 0x1E 16 read-only n 0x0 0x0 RESULT Filter Result 0 16 RESULT[0] Filter Result 0x38 16 read-only n 0x0 0x0 RESULT Filter Result 0 16 RESULT[1] Filter Result 0x56 16 read-only n 0x0 0x0 RESULT Filter Result 0 16 STATUS Status 0x7 8 read-only n 0x0 0x0 EOC0 DAC 0 End of Conversion 2 1 EOC1 DAC 1 End of Conversion 3 1 READY0 DAC 0 Startup Ready 0 1 READY1 DAC 1 Startup Ready 1 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 DATA0 Data DAC 0 2 1 DATA1 Data DAC 1 3 1 DATABUF0 Data Buffer DAC 0 4 1 DATABUF1 Data Buffer DAC 1 5 1 ENABLE DAC Enable Status 1 1 SWRST Software Reset 0 1 DMAC Direct Memory Access Controller DMAC 0x0 0x0 0x360 registers n DMAC_0 31 DMAC_1 32 DMAC_2 33 DMAC_3 34 DMAC_OTHER 35 ACTIVE Active Channel and Levels 0x30 32 read-only n 0x0 0x0 ABUSY Active Channel Busy 15 1 BTCNT Active Channel Block Transfer Count 16 16 ID Active Channel ID 8 5 LVLEX0 Level 0 Channel Trigger Request Executing 0 1 LVLEX1 Level 1 Channel Trigger Request Executing 1 1 LVLEX2 Level 2 Channel Trigger Request Executing 2 1 LVLEX3 Level 3 Channel Trigger Request Executing 3 1 BASEADDR Descriptor Memory Section Base Address 0x34 32 read-write n 0x0 0x0 BASEADDR Descriptor Memory Base Address 0 32 BUSYCH Busy Channels 0x28 32 read-only n 0x0 0x0 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH10 Busy Channel 10 10 1 BUSYCH11 Busy Channel 11 11 1 BUSYCH12 Busy Channel 12 12 1 BUSYCH13 Busy Channel 13 13 1 BUSYCH14 Busy Channel 14 14 1 BUSYCH15 Busy Channel 15 15 1 BUSYCH16 Busy Channel 16 16 1 BUSYCH17 Busy Channel 17 17 1 BUSYCH18 Busy Channel 18 18 1 BUSYCH19 Busy Channel 19 19 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH20 Busy Channel 20 20 1 BUSYCH21 Busy Channel 21 21 1 BUSYCH22 Busy Channel 22 22 1 BUSYCH23 Busy Channel 23 23 1 BUSYCH24 Busy Channel 24 24 1 BUSYCH25 Busy Channel 25 25 1 BUSYCH26 Busy Channel 26 26 1 BUSYCH27 Busy Channel 27 27 1 BUSYCH28 Busy Channel 28 28 1 BUSYCH29 Busy Channel 29 29 1 BUSYCH3 Busy Channel 3 3 1 BUSYCH30 Busy Channel 30 30 1 BUSYCH31 Busy Channel 31 31 1 BUSYCH4 Busy Channel 4 4 1 BUSYCH5 Busy Channel 5 5 1 BUSYCH6 Busy Channel 6 6 1 BUSYCH7 Busy Channel 7 7 1 BUSYCH8 Busy Channel 8 8 1 BUSYCH9 Busy Channel 9 9 1 CHANNEL[0]-CHCTRLA Channel n Control A 0x40 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[0]-CHCTRLB Channel n Control B 0x44 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[0]-CHEVCTRL Channel n Event Control 0x46 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x4C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x4D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x4E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[0]-CHPRILVL Channel n Priority Level 0x45 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[0]-CHSTATUS Channel n Status 0x4F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x630 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x634 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x636 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x63C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x63D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x63E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x635 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x63F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x720 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x724 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x726 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x72C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x72D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x72E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x725 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x72F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x820 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x824 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x826 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x82C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x82D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x82E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x825 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x82F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x930 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x934 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x936 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x93C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x93D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x93E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x935 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x93F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0xA50 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0xA54 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0xA56 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xA5C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xA5D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xA5E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0xA55 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xA5F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0xB80 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0xB84 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0xB86 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xB8C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xB8D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xB8E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0xB85 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xB8F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0xCC0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0xCC4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0xCC6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xCCC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xCCD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xCCE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0xCC5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xCCF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0xE10 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0xE14 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0xE16 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xE1C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xE1D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xE1E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0xE15 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xE1F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0xF70 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0xF74 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0xF76 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xF7C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xF7D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xF7E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0xF75 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xF7F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x10E0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x10E4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x10E6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x10EC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x10ED 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x10EE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x10E5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x10EF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x90 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x94 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x96 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x9C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x9D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x9E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x95 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x9F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1260 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1264 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1266 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x126C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x126D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x126E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1265 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x126F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x13F0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x13F4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x13F6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x13FC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x13FD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x13FE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x13F5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x13FF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1590 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1594 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1596 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x159C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x159D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x159E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1595 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x159F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1740 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1744 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1746 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x174C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x174D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x174E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1745 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x174F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1900 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1904 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1906 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x190C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x190D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x190E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1905 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x190F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1AD0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1AD4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1AD6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1ADC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1ADD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1ADE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1AD5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1ADF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1CB0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1CB4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1CB6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1CBC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1CBD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1CBE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1CB5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1CBF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1EA0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1EA4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1EA6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1EAC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1EAD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1EAE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1EA5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1EAF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x20A0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x20A4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x20A6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x20AC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x20AD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x20AE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x20A5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x20AF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x22B0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x22B4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x22B6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x22BC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x22BD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x22BE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x22B5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x22BF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0xF0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0xF4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0xF6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xFC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xFD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xFE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0xF5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xFF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x24D0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x24D4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x24D6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x24DC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x24DD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x24DE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x24D5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x24DF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x2700 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x2704 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x2706 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x270C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x270D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x270E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x2705 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x270F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x160 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x164 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x166 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x16C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x16D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x16E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x165 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x16F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x1E0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x1E4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x1E6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1EC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1ED 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1EE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x1E5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1EF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x270 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x274 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x276 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x27C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x27D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x27E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x275 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x27F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x310 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x314 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x316 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x31C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x31D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x31E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x315 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x31F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x3C0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x3C4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x3C6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x3CC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x3CD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x3CE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x3C5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x3CF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x480 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x484 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x486 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x48C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x48D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x48E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x485 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x48F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLA Channel n Control A 0x550 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHCTRLB Channel n Control B 0x554 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0 SUSPEND Channel suspend operation 1 RESUME Channel resume operation 2 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHEVCTRL Channel n Event Control 0x556 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x55C 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x55D 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x55E 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHPRILVL Channel n Priority Level 0x555 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x55F 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CHCTRLA Channel n Control A 0x0 32 read-write n 0x0 0x0 BURSTLEN Burst Length 24 4 BURSTLENSelect SINGLE Single-beat burst length 0 2BEAT 2-beats burst length 1 11BEAT 11-beats burst length 10 12BEAT 12-beats burst length 11 13BEAT 13-beats burst length 12 14BEAT 14-beats burst length 13 15BEAT 15-beats burst length 14 16BEAT 16-beats burst length 15 3BEAT 3-beats burst length 2 4BEAT 4-beats burst length 3 5BEAT 5-beats burst length 4 6BEAT 6-beats burst length 5 7BEAT 7-beats burst length 6 8BEAT 8-beats burst length 7 9BEAT 9-beats burst length 8 10BEAT 10-beats burst length 9 ENABLE Channel Enable 1 1 RUNSTDBY Channel Run in Standby 6 1 SWRST Channel Software Reset 0 1 THRESHOLD FIFO Threshold 28 2 THRESHOLDSelect 1BEAT Destination write starts after each beat source address read 0 2BEATS Destination write starts after 2-beats source address read 1 4BEATS Destination write starts after 4-beats source address read 2 8BEATS Destination write starts after 8-beats source address read 3 TRIGACT Trigger Action 20 2 TRIGACTSelect BLOCK One trigger required for each block transfer 0 BURST One trigger required for each burst transfer 2 TRANSACTION One trigger required for each transaction 3 TRIGSRC Trigger Source 8 7 TRIGSRCSelect DISABLE Only software/event triggers 0 CHCTRLB Channel n Control B 0x4 8 read-write n 0x0 0x0 CMD Software Command 0 2 CMDSelect NOACT No action 0x0 SUSPEND Channel suspend operation 0x1 RESUME Channel resume operation 0x2 CHEVCTRL Channel n Event Control 0x6 8 read-write n 0x0 0x0 EVACT Channel Event Input Action 0 3 EVACTSelect NOACT No action 0 TRIG Transfer and periodic transfer trigger 1 CTRIG Conditional transfer trigger 2 CBLOCK Conditional block transfer 3 SUSPEND Channel suspend operation 4 RESUME Channel resume operation 5 SSKIP Skip next block suspend action 6 INCPRI Increase priority 7 EVIE Channel Event Input Enable 6 1 EVOE Channel Event Output Enable 7 1 EVOMODE Channel Event Output Mode 4 2 EVOMODESelect DEFAULT Block event output selection. Refer to BTCTRL.EVOSEL for available selections. 0 TRIGACT Ongoing trigger action 1 CHINTENCLR Channel n Interrupt Enable Clear 0xC 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHINTENSET Channel n Interrupt Enable Set 0xD 8 read-write n 0x0 0x0 SUSP Channel Suspend Interrupt Enable 2 1 TCMPL Channel Transfer Complete Interrupt Enable 1 1 TERR Channel Transfer Error Interrupt Enable 0 1 CHINTFLAG Channel n Interrupt Flag Status and Clear 0xE 8 read-write n 0x0 0x0 SUSP Channel Suspend 2 1 TCMPL Channel Transfer Complete 1 1 TERR Channel Transfer Error 0 1 CHPRILVL Channel n Priority Level 0x5 8 read-write n 0x0 0x0 PRILVL Channel Priority Level 0 2 PRILVLSelect LVL0 Channel Priority Level 0 (Lowest Level) 0 LVL1 Channel Priority Level 1 1 LVL2 Channel Priority Level 2 2 LVL3 Channel Priority Level 3 (Highest Level) 3 CHSTATUS Channel n Status 0xF 8 read-write n 0x0 0x0 BUSY Channel Busy 1 1 CRCERR Channel CRC Error 3 1 FERR Channel Fetch Error 2 1 PEND Channel Pending 0 1 CRCCHKSUM CRC Checksum 0x8 32 read-write n 0x0 0x0 CRCCHKSUM CRC Checksum 0 32 CRCCTRL CRC Control 0x2 16 read-write n 0x0 0x0 CRCBEATSIZE CRC Beat Size 0 2 CRCBEATSIZESelect BYTE 8-bit bus transfer 0 HWORD 16-bit bus transfer 1 WORD 32-bit bus transfer 2 CRCMODE CRC Operating Mode 14 2 CRCMODESelect DEFAULT Default operating mode 0 CRCMON Memory CRC monitor operating mode 2 CRCGEN Memory CRC generation operating mode 3 CRCPOLY CRC Polynomial Type 2 2 CRCPOLYSelect CRC16 CRC-16 (CRC-CCITT) 0 CRC32 CRC32 (IEEE 802.3) 1 CRCSRC CRC Input Source 8 6 CRCSRCSelect DISABLE CRC Disabled 0 IO I/O interface 1 CRCDATAIN CRC Data Input 0x4 32 read-write n 0x0 0x0 CRCDATAIN CRC Data Input 0 32 CRCSTATUS CRC Status 0xC 8 read-write n 0x0 0x0 CRCBUSY CRC Module Busy 0 1 CRCERR CRC Error 2 1 CRCZERO CRC Zero 1 1 CTRL Control 0x0 16 read-write n 0x0 0x0 DMAENABLE DMA Enable 1 1 LVLEN0 Priority Level 0 Enable 8 1 LVLEN1 Priority Level 1 Enable 9 1 LVLEN2 Priority Level 2 Enable 10 1 LVLEN3 Priority Level 3 Enable 11 1 SWRST Software Reset 0 1 DBGCTRL Debug Control 0xD 8 read-write n 0x0 0x0 DBGRUN Debug Run 0 1 INTPEND Interrupt Pending 0x20 16 read-write n 0x0 0x0 BUSY Busy 14 1 CRCERR CRC Error 12 1 FERR Fetch Error 13 1 ID Channel ID 0 5 PEND Pending 15 1 SUSP Channel Suspend 10 1 TCMPL Transfer Complete 9 1 TERR Transfer Error 8 1 INTSTATUS Interrupt Status 0x24 32 read-only n 0x0 0x0 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT10 Channel 10 Pending Interrupt 10 1 CHINT11 Channel 11 Pending Interrupt 11 1 CHINT12 Channel 12 Pending Interrupt 12 1 CHINT13 Channel 13 Pending Interrupt 13 1 CHINT14 Channel 14 Pending Interrupt 14 1 CHINT15 Channel 15 Pending Interrupt 15 1 CHINT16 Channel 16 Pending Interrupt 16 1 CHINT17 Channel 17 Pending Interrupt 17 1 CHINT18 Channel 18 Pending Interrupt 18 1 CHINT19 Channel 19 Pending Interrupt 19 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT20 Channel 20 Pending Interrupt 20 1 CHINT21 Channel 21 Pending Interrupt 21 1 CHINT22 Channel 22 Pending Interrupt 22 1 CHINT23 Channel 23 Pending Interrupt 23 1 CHINT24 Channel 24 Pending Interrupt 24 1 CHINT25 Channel 25 Pending Interrupt 25 1 CHINT26 Channel 26 Pending Interrupt 26 1 CHINT27 Channel 27 Pending Interrupt 27 1 CHINT28 Channel 28 Pending Interrupt 28 1 CHINT29 Channel 29 Pending Interrupt 29 1 CHINT3 Channel 3 Pending Interrupt 3 1 CHINT30 Channel 30 Pending Interrupt 30 1 CHINT31 Channel 31 Pending Interrupt 31 1 CHINT4 Channel 4 Pending Interrupt 4 1 CHINT5 Channel 5 Pending Interrupt 5 1 CHINT6 Channel 6 Pending Interrupt 6 1 CHINT7 Channel 7 Pending Interrupt 7 1 CHINT8 Channel 8 Pending Interrupt 8 1 CHINT9 Channel 9 Pending Interrupt 9 1 PENDCH Pending Channels 0x2C 32 read-only n 0x0 0x0 PENDCH0 Pending Channel 0 0 1 PENDCH1 Pending Channel 1 1 1 PENDCH10 Pending Channel 10 10 1 PENDCH11 Pending Channel 11 11 1 PENDCH12 Pending Channel 12 12 1 PENDCH13 Pending Channel 13 13 1 PENDCH14 Pending Channel 14 14 1 PENDCH15 Pending Channel 15 15 1 PENDCH16 Pending Channel 16 16 1 PENDCH17 Pending Channel 17 17 1 PENDCH18 Pending Channel 18 18 1 PENDCH19 Pending Channel 19 19 1 PENDCH2 Pending Channel 2 2 1 PENDCH20 Pending Channel 20 20 1 PENDCH21 Pending Channel 21 21 1 PENDCH22 Pending Channel 22 22 1 PENDCH23 Pending Channel 23 23 1 PENDCH24 Pending Channel 24 24 1 PENDCH25 Pending Channel 25 25 1 PENDCH26 Pending Channel 26 26 1 PENDCH27 Pending Channel 27 27 1 PENDCH28 Pending Channel 28 28 1 PENDCH29 Pending Channel 29 29 1 PENDCH3 Pending Channel 3 3 1 PENDCH30 Pending Channel 30 30 1 PENDCH31 Pending Channel 31 31 1 PENDCH4 Pending Channel 4 4 1 PENDCH5 Pending Channel 5 5 1 PENDCH6 Pending Channel 6 6 1 PENDCH7 Pending Channel 7 7 1 PENDCH8 Pending Channel 8 8 1 PENDCH9 Pending Channel 9 9 1 PRICTRL0 Priority Control 0 0x14 32 read-write n 0x0 0x0 LVLPRI0 Level 0 Channel Priority Number 0 5 LVLPRI1 Level 1 Channel Priority Number 8 5 LVLPRI2 Level 2 Channel Priority Number 16 5 LVLPRI3 Level 3 Channel Priority Number 24 5 QOS0 Level 0 Quality of Service 5 2 QOS0Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 QOS1 Level 1 Quality of Service 13 2 QOS1Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 QOS2 Level 2 Quality of Service 21 2 QOS2Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 QOS3 Level 3 Quality of Service 29 2 QOS3Select REGULAR Regular delivery 0 SHORTAGE Bandwidth shortage 1 SENSITIVE Latency sensitive 2 CRITICAL Latency critical 3 RRLVLEN0 Level 0 Round-Robin Scheduling Enable 7 1 RRLVLEN1 Level 1 Round-Robin Scheduling Enable 15 1 RRLVLEN2 Level 2 Round-Robin Scheduling Enable 23 1 RRLVLEN3 Level 3 Round-Robin Scheduling Enable 31 1 SWTRIGCTRL Software Trigger Control 0x10 32 read-write n 0x0 0x0 SWTRIG0 Channel 0 Software Trigger 0 1 SWTRIG1 Channel 1 Software Trigger 1 1 SWTRIG10 Channel 10 Software Trigger 10 1 SWTRIG11 Channel 11 Software Trigger 11 1 SWTRIG12 Channel 12 Software Trigger 12 1 SWTRIG13 Channel 13 Software Trigger 13 1 SWTRIG14 Channel 14 Software Trigger 14 1 SWTRIG15 Channel 15 Software Trigger 15 1 SWTRIG16 Channel 16 Software Trigger 16 1 SWTRIG17 Channel 17 Software Trigger 17 1 SWTRIG18 Channel 18 Software Trigger 18 1 SWTRIG19 Channel 19 Software Trigger 19 1 SWTRIG2 Channel 2 Software Trigger 2 1 SWTRIG20 Channel 20 Software Trigger 20 1 SWTRIG21 Channel 21 Software Trigger 21 1 SWTRIG22 Channel 22 Software Trigger 22 1 SWTRIG23 Channel 23 Software Trigger 23 1 SWTRIG24 Channel 24 Software Trigger 24 1 SWTRIG25 Channel 25 Software Trigger 25 1 SWTRIG26 Channel 26 Software Trigger 26 1 SWTRIG27 Channel 27 Software Trigger 27 1 SWTRIG28 Channel 28 Software Trigger 28 1 SWTRIG29 Channel 29 Software Trigger 29 1 SWTRIG3 Channel 3 Software Trigger 3 1 SWTRIG30 Channel 30 Software Trigger 30 1 SWTRIG31 Channel 31 Software Trigger 31 1 SWTRIG4 Channel 4 Software Trigger 4 1 SWTRIG5 Channel 5 Software Trigger 5 1 SWTRIG6 Channel 6 Software Trigger 6 1 SWTRIG7 Channel 7 Software Trigger 7 1 SWTRIG8 Channel 8 Software Trigger 8 1 SWTRIG9 Channel 9 Software Trigger 9 1 WRBADDR Write-Back Memory Section Base Address 0x38 32 read-write n 0x0 0x0 WRBADDR Write-Back Memory Base Address 0 32 DSU Device Service Unit DSU 0x0 0x0 0x2000 registers n ADDR Address 0x4 32 read-write n 0x0 0x0 ADDR Address 2 30 AMOD Access Mode 0 2 CFG Configuration 0x1C 32 read-write n 0x0 0x0 DCCDMALEVEL DMA Trigger Level 2 2 DCCDMALEVELSelect EMPTY Trigger rises when DCC is empty 0 FULL Trigger rises when DCC is full 1 ETBRAMEN Trace Control 4 1 LQOS Latency Quality Of Service 0 2 CID0 Component Identification 0 0x1FF0 32 read-only n 0x0 0x0 PREAMBLEB0 Preamble Byte 0 0 8 CID1 Component Identification 1 0x1FF4 32 read-only n 0x0 0x0 CCLASS Component Class 4 4 PREAMBLE Preamble 0 4 CID2 Component Identification 2 0x1FF8 32 read-only n 0x0 0x0 PREAMBLEB2 Preamble Byte 2 0 8 CID3 Component Identification 3 0x1FFC 32 read-only n 0x0 0x0 PREAMBLEB3 Preamble Byte 3 0 8 CTRL Control 0x0 8 write-only n 0x0 0x0 ARR Auxiliary Row Read 6 1 CE Chip-Erase 4 1 CRC 32-bit Cyclic Redundancy Code 2 1 MBIST Memory built-in self-test 3 1 SMSA Start Memory Stream Access 7 1 SWRST Software Reset 0 1 DATA Data 0xC 32 read-write n 0x0 0x0 DATA Data 0 32 DCC0 Debug Communication Channel n 0x10 32 read-write n 0x0 0x0 DATA Data 0 32 DCC1 Debug Communication Channel n 0x14 32 read-write n 0x0 0x0 DATA Data 0 32 DCC[0] Debug Communication Channel n 0x20 32 read-write n 0x0 0x0 DATA Data 0 32 DCC[1] Debug Communication Channel n 0x34 32 read-write n 0x0 0x0 DATA Data 0 32 DCFG0 Device Configuration 0xF0 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DCFG1 Device Configuration 0xF4 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DCFG[0] Device Configuration 0x1E0 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DCFG[1] Device Configuration 0x2D4 32 read-write n 0x0 0x0 DCFG Device Configuration 0 32 DID Device Identification 0x18 32 read-only n 0x0 0x0 DEVSEL Device Select 0 8 DIE Die Number 12 4 FAMILY Family 23 5 FAMILYSelect 0 General purpose microcontroller 0 1 PicoPower 1 PROCESSOR Processor 28 4 PROCESSORSelect CM0P Cortex-M0+ 1 CM23 Cortex-M23 2 CM3 Cortex-M3 3 CM4 Cortex-M4 5 CM4F Cortex-M4 with FPU 6 CM33 Cortex-M33 7 REVISION Revision Number 8 4 SERIES Series 16 6 SERIESSelect 0 Cortex-M0+ processor, basic feature set 0 1 Cortex-M0+ processor, USB 1 END CoreSight ROM Table End 0x1008 32 read-only n 0x0 0x0 END End Marker 0 32 ENTRY0 CoreSight ROM Table Entry 0 0x1000 32 read-only n 0x0 0x0 ADDOFF Address Offset 12 20 EPRES Entry Present 0 1 FMT Format 1 1 ENTRY1 CoreSight ROM Table Entry 1 0x1004 32 read-only n 0x0 0x0 LENGTH Length 0x8 32 read-write n 0x0 0x0 LENGTH Length 2 30 MEMTYPE CoreSight ROM Table Memory Type 0x1FCC 32 read-only n 0x0 0x0 SMEMP System Memory Present 0 1 PID0 Peripheral Identification 0 0x1FE0 32 read-only n 0x0 0x0 PARTNBL Part Number Low 0 8 PID1 Peripheral Identification 1 0x1FE4 32 read-only n 0x0 0x0 JEPIDCL Low part of the JEP-106 Identity Code 4 4 PARTNBH Part Number High 0 4 PID2 Peripheral Identification 2 0x1FE8 32 read-only n 0x0 0x0 JEPIDCH JEP-106 Identity Code High 0 3 JEPU JEP-106 Identity Code is used 3 1 REVISION Revision Number 4 4 PID3 Peripheral Identification 3 0x1FEC 32 read-only n 0x0 0x0 CUSMOD ARM CUSMOD 0 4 REVAND Revision Number 4 4 PID4 Peripheral Identification 4 0x1FD0 32 read-only n 0x0 0x0 FKBC 4KB count 4 4 JEPCC JEP-106 Continuation Code 0 4 PID5 Peripheral Identification 5 0x1FD4 32 read-only n 0x0 0x0 PID6 Peripheral Identification 6 0x1FD8 32 read-only n 0x0 0x0 PID7 Peripheral Identification 7 0x1FDC 32 read-only n 0x0 0x0 STATUSA Status A 0x1 8 read-write n 0x0 0x0 BERR Bus Error 2 1 CRSTEXT CPU Reset Phase Extension 1 1 DONE Done 0 1 FAIL Failure 3 1 PERR Protection Error 4 1 STATUSB Status B 0x2 8 read-only n 0x0 0x0 CELCK Chip Erase Locked 5 1 DBGPRES Debugger Present 1 1 DCCD0 Debug Communication Channel 0 Dirty 2 1 DCCD1 Debug Communication Channel 1 Dirty 3 1 HPE Hot-Plugging Enable 4 1 PROT Protected 0 1 TDCCD0 Test Debug Communication Channel 0 Dirty 6 1 TDCCD1 Test Debug Communication Channel 1 Dirty 7 1 DWT Data Watchpoint and Trace Register DWT 0x0 0x0 0x5C registers n COMP0 Comparator Register 0 0x20 32 read-write n 0x0 0x0 COMP1 Comparator Register 1 0x30 32 read-write n 0x0 0x0 COMP2 Comparator Register 2 0x40 32 read-write n 0x0 0x0 COMP3 Comparator Register 3 0x50 32 read-write n 0x0 0x0 CPICNT CPI Count Register 0x8 32 read-write n 0x0 0x0 CPICNT 0 8 CTRL Control Register 0x0 32 read-write n 0x0 0x0 CPIEVTENA 17 1 CYCCNTENA 0 1 CYCEVTENA 22 1 CYCTAP 9 1 EXCEVTENA 18 1 EXCTRCENA 16 1 FOLDEVTENA 21 1 LSUEVTENA 20 1 NOCYCCNT 25 1 NOEXTTRIG 26 1 NOPRFCNT 24 1 NOTRCPKT 27 1 NUMCOMP 28 4 PCSAMPLENA 12 1 POSTINIT 5 4 POSTPRESET 1 4 SLEEPEVTENA 19 1 SYNCTAP 10 2 CYCCNT Cycle Count Register 0x4 32 read-write n 0x0 0x0 EXCCNT Exception Overhead Count Register 0xC 32 read-write n 0x0 0x0 EXCCNT 0 8 FOLDCNT Folded-instruction Count Register 0x18 32 read-write n 0x0 0x0 FOLDCNT 0 8 FUNCTION0 Function Register 0 0x28 32 read-write n 0x0 0x0 CYCMATCH 7 1 DATAVADDR0 12 4 DATAVADDR1 16 4 DATAVMATCH 8 1 DATAVSIZE 10 2 EMITRANGE 5 1 FUNCTION 0 4 LNK1ENA 9 1 MATCHED 24 1 FUNCTION1 Function Register 1 0x38 32 read-write n 0x0 0x0 CYCMATCH 7 1 DATAVADDR0 12 4 DATAVADDR1 16 4 DATAVMATCH 8 1 DATAVSIZE 10 2 EMITRANGE 5 1 FUNCTION 0 4 LNK1ENA 9 1 MATCHED 24 1 FUNCTION2 Function Register 2 0x48 32 read-write n 0x0 0x0 CYCMATCH 7 1 DATAVADDR0 12 4 DATAVADDR1 16 4 DATAVMATCH 8 1 DATAVSIZE 10 2 EMITRANGE 5 1 FUNCTION 0 4 LNK1ENA 9 1 MATCHED 24 1 FUNCTION3 Function Register 3 0x58 32 read-write n 0x0 0x0 CYCMATCH 7 1 DATAVADDR0 12 4 DATAVADDR1 16 4 DATAVMATCH 8 1 DATAVSIZE 10 2 EMITRANGE 5 1 FUNCTION 0 4 LNK1ENA 9 1 MATCHED 24 1 LSUCNT LSU Count Register 0x14 32 read-write n 0x0 0x0 LSUCNT 0 8 MASK0 Mask Register 0 0x24 32 read-write n 0x0 0x0 MASK 0 5 MASK1 Mask Register 1 0x34 32 read-write n 0x0 0x0 MASK 0 5 MASK2 Mask Register 2 0x44 32 read-write n 0x0 0x0 MASK 0 5 MASK3 Mask Register 3 0x54 32 read-write n 0x0 0x0 MASK 0 5 PCSR Program Counter Sample Register 0x1C 32 read-only n 0x0 0x0 SLEEPCNT Sleep Count Register 0x10 32 read-write n 0x0 0x0 SLEEPCNT 0 8 EIC External Interrupt Controller EIC 0x0 0x0 0x3C registers n EIC_EXTINT_0 12 EIC_EXTINT_1 13 EIC_EXTINT_2 14 EIC_EXTINT_3 15 EIC_EXTINT_4 16 EIC_EXTINT_5 17 EIC_EXTINT_6 18 EIC_EXTINT_7 19 EIC_EXTINT_8 20 EIC_EXTINT_9 21 EIC_EXTINT_10 22 EIC_EXTINT_11 23 EIC_EXTINT_12 24 EIC_EXTINT_13 25 EIC_EXTINT_14 26 EIC_EXTINT_15 27 ASYNCH External Interrupt Asynchronous Mode 0x18 32 read-write n 0x0 0x0 ASYNCH Asynchronous Edge Detection Mode 0 16 ASYNCHSelect SYNC Edge detection is clock synchronously operated 0 ASYNC Edge detection is clock asynchronously operated 1 CONFIG0 External Interrupt Sense Configuration 0x1C 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 CONFIG1 External Interrupt Sense Configuration 0x20 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 CONFIG[0] External Interrupt Sense Configuration 0x38 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 CONFIG[1] External Interrupt Sense Configuration 0x58 32 read-write n 0x0 0x0 FILTEN0 Filter Enable 0 3 1 FILTEN1 Filter Enable 1 7 1 FILTEN2 Filter Enable 2 11 1 FILTEN3 Filter Enable 3 15 1 FILTEN4 Filter Enable 4 19 1 FILTEN5 Filter Enable 5 23 1 FILTEN6 Filter Enable 6 27 1 FILTEN7 Filter Enable 7 31 1 SENSE0 Input Sense Configuration 0 0 3 SENSE0Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE1 Input Sense Configuration 1 4 3 SENSE1Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE2 Input Sense Configuration 2 8 3 SENSE2Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE3 Input Sense Configuration 3 12 3 SENSE3Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE4 Input Sense Configuration 4 16 3 SENSE4Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE5 Input Sense Configuration 5 20 3 SENSE5Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE6 Input Sense Configuration 6 24 3 SENSE6Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 SENSE7 Input Sense Configuration 7 28 3 SENSE7Select NONE No detection 0 RISE Rising edge detection 1 FALL Falling edge detection 2 BOTH Both edges detection 3 HIGH High level detection 4 LOW Low level detection 5 CTRLA Control A 0x0 8 read-write n 0x0 0x0 CKSEL Clock Selection 4 1 CKSELSelect CLK_GCLK Clocked by GCLK 0 CLK_ULP32K Clocked by ULP32K 1 ENABLE Enable 1 1 SWRST Software Reset 0 1 DEBOUNCEN Debouncer Enable 0x30 32 read-write n 0x0 0x0 DEBOUNCEN Debouncer Enable 0 16 DPRESCALER Debouncer Prescaler 0x34 32 read-write n 0x0 0x0 PRESCALER0 Debouncer Prescaler 0 3 PRESCALER0Select DIV2 EIC clock divided by 2 0 DIV4 EIC clock divided by 4 1 DIV8 EIC clock divided by 8 2 DIV16 EIC clock divided by 16 3 DIV32 EIC clock divided by 32 4 DIV64 EIC clock divided by 64 5 DIV128 EIC clock divided by 128 6 DIV256 EIC clock divided by 256 7 PRESCALER1 Debouncer Prescaler 4 3 PRESCALER1Select DIV2 EIC clock divided by 2 0 DIV4 EIC clock divided by 4 1 DIV8 EIC clock divided by 8 2 DIV16 EIC clock divided by 16 3 DIV32 EIC clock divided by 32 4 DIV64 EIC clock divided by 64 5 DIV128 EIC clock divided by 128 6 DIV256 EIC clock divided by 256 7 STATES0 Debouncer number of states 3 1 STATES0Select LFREQ3 3 low frequency samples 0 LFREQ7 7 low frequency samples 1 STATES1 Debouncer number of states 7 1 STATES1Select LFREQ3 3 low frequency samples 0 LFREQ7 7 low frequency samples 1 TICKON Pin Sampler frequency selection 16 1 TICKONSelect CLK_GCLK_EIC Clocked by GCLK 0 CLK_LFREQ Clocked by Low Frequency Clock 1 EVCTRL Event Control 0x8 32 read-write n 0x0 0x0 EXTINTEO External Interrupt Event Output Enable 0 16 INTENCLR Interrupt Enable Clear 0xC 32 read-write n 0x0 0x0 EXTINT External Interrupt Enable 0 16 INTENSET Interrupt Enable Set 0x10 32 read-write n 0x0 0x0 EXTINT External Interrupt Enable 0 16 INTFLAG Interrupt Flag Status and Clear 0x14 32 read-write n 0x0 0x0 EXTINT External Interrupt 0 16 NMICTRL Non-Maskable Interrupt Control 0x1 8 read-write n 0x0 0x0 NMIASYNCH Asynchronous Edge Detection Mode 4 1 NMIASYNCHSelect SYNC Edge detection is clock synchronously operated 0 ASYNC Edge detection is clock asynchronously operated 1 NMIFILTEN Non-Maskable Interrupt Filter Enable 3 1 NMISENSE Non-Maskable Interrupt Sense Configuration 0 3 NMISENSESelect NONE No detection 0 RISE Rising-edge detection 1 FALL Falling-edge detection 2 BOTH Both-edges detection 3 HIGH High-level detection 4 LOW Low-level detection 5 NMIFLAG Non-Maskable Interrupt Flag Status and Clear 0x2 16 read-write n 0x0 0x0 NMI Non-Maskable Interrupt 0 1 PINSTATE Pin State 0x38 32 read-only n 0x0 0x0 PINSTATE Pin State 0 16 SYNCBUSY Synchronization Busy 0x4 32 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy Status 1 1 SWRST Software Reset Synchronization Busy Status 0 1 ETM Embedded Trace Macrocell ETM 0x0 0x0 0x1000 registers n AUTHSTATUS ETM Authentication Status Register 0xFB8 32 read-only n 0x0 0x0 CCER ETM Configuration Code Extension Register 0x1E8 32 read-only n 0x0 0x0 CCR ETM Configuration Code Register 0x4 32 read-only n 0x0 0x0 CIDR0 ETM Component Identification Register #0 0xFF0 32 read-only n 0x0 0x0 CIDR1 ETM Component Identification Register #1 0xFF4 32 read-only n 0x0 0x0 CIDR2 ETM Component Identification Register #2 0xFF8 32 read-only n 0x0 0x0 CIDR3 ETM Component Identification Register #3 0xFFC 32 read-only n 0x0 0x0 CLAIMCLR ETM Claim Tag Clear Register 0xFA4 32 read-write n 0x0 0x0 CLAIMSET ETM Claim Tag Set Register 0xFA0 32 read-write n 0x0 0x0 CNTRLDVR1 ETM Free-running Counter Reload Value 0x140 32 read-write n 0x0 0x0 CR ETM Main Control Register 0x0 32 read-write n 0x0 0x0 BROUT Branch Output 8 1 DBGRQ Debug Request Control 9 1 ETMPD ETM Power Down 0 1 PORTMODE Port Mode bits 1:0 16 2 PORTMODE2 Port Mode bit 2 13 1 PORTSEL ETM Port Select 11 1 PORTSIZE Port Size bits 2:0 4 3 PORTSIZE3 Port Size bit 3 21 1 PROG ETM Programming 10 1 STALL Stall Processor 7 1 TSEN TimeStamp Enable 28 1 DEVTYPE ETM CoreSight Device Type Register 0xFCC 32 read-only n 0x0 0x0 FFLR ETM FIFO Full Level Register 0x28 32 read-write n 0x0 0x0 IDR ETM ID Register 0x1E4 32 read-only n 0x0 0x0 IDR2 ETM ID Register 2 0x208 32 read-only n 0x0 0x0 ITATBCTR0 ETM Integration Test ATB Control 0 0xEF8 32 write-only n 0x0 0x0 ITATBCTR2 ETM Integration Test ATB Control 2 0xEF0 32 read-only n 0x0 0x0 ITCTRL ETM Integration Mode Control Register 0xF00 32 read-write n 0x0 0x0 INTEGRATION 0 1 ITMISCIN ETM Integration Test Miscellaneous Inputs 0xEE0 32 read-only n 0x0 0x0 ITTRIGOUT ETM Integration Test Trigger Out 0xEE8 32 write-only n 0x0 0x0 LAR ETM Lock Access Register 0xFB0 32 write-only n 0x0 0x0 LSR ETM Lock Status Register 0xFB4 32 read-only n 0x0 0x0 Access 1 1 ByteAcc 2 1 Present 0 1 PDSR ETM Device Power-Down Status Register 0x314 32 read-only n 0x0 0x0 PIDR0 ETM Peripheral Identification Register #0 0xFE0 32 read-only n 0x0 0x0 PIDR1 ETM Peripheral Identification Register #1 0xFE4 32 read-only n 0x0 0x0 PIDR2 ETM Peripheral Identification Register #2 0xFE8 32 read-only n 0x0 0x0 PIDR3 ETM Peripheral Identification Register #3 0xFEC 32 read-only n 0x0 0x0 PIDR4 ETM Peripheral Identification Register #4 0xFD0 32 read-only n 0x0 0x0 PIDR5 ETM Peripheral Identification Register #5 0xFD4 32 read-only n 0x0 0x0 PIDR6 ETM Peripheral Identification Register #6 0xFD8 32 read-only n 0x0 0x0 PIDR7 ETM Peripheral Identification Register #7 0xFDC 32 read-only n 0x0 0x0 SCR ETM System Configuration Register 0x14 32 read-only n 0x0 0x0 SR ETM Status Register 0x10 32 read-write n 0x0 0x0 SYNCFR ETM Synchronization Frequency Register 0x1E0 32 read-only n 0x0 0x0 TECR1 ETM TraceEnable Control 1 Register 0x24 32 read-write n 0x0 0x0 TEEVR ETM TraceEnable Event Register 0x20 32 read-write n 0x0 0x0 TESSEICR ETM TraceEnable Start/Stop EmbeddedICE Control Register 0x1F0 32 read-write n 0x0 0x0 TRACEIDR ETM CoreSight Trace ID Register 0x200 32 read-write n 0x0 0x0 TRIGGER ETM Trigger Event Register 0x8 32 read-write n 0x0 0x0 TSEVT ETM TimeStamp Event Register 0x1F8 32 read-write n 0x0 0x0 EVSYS Event System Interface EVSYS 0x0 0x0 0x2BC registers n EVSYS_0 36 EVSYS_1 37 EVSYS_2 38 EVSYS_3 39 EVSYS_OTHER 40 BUSYCH Busy Channels 0x18 32 read-only n 0x0 0x0 BUSYCH0 Busy Channel 0 0 1 BUSYCH1 Busy Channel 1 1 1 BUSYCH10 Busy Channel 10 10 1 BUSYCH11 Busy Channel 11 11 1 BUSYCH2 Busy Channel 2 2 1 BUSYCH3 Busy Channel 3 3 1 BUSYCH4 Busy Channel 4 4 1 BUSYCH5 Busy Channel 5 5 1 BUSYCH6 Busy Channel 6 6 1 BUSYCH7 Busy Channel 7 7 1 BUSYCH8 Busy Channel 8 8 1 BUSYCH9 Busy Channel 9 9 1 CHANNEL Channel n Control 0x0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[0]-CHANNEL Channel n Control 0x20 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x24 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x25 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x26 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[0]-CHSTATUS Channel n Status 0x27 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x318 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x31C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x31D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x31E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x31F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x390 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x394 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x395 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x396 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x397 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x410 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x414 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x415 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x416 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x417 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x498 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x49C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x49D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x49E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x49F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x528 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x52C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x52D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x52E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x52F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x5C0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x5C4 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x5C5 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x5C6 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x5C7 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x660 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x664 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x665 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x666 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x667 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x708 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x70C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x70D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x70E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x70F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x7B8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x7BC 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x7BD 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x7BE 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x7BF 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x870 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x874 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x875 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x876 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x877 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x48 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x4C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x4D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x4E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x4F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x930 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x934 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x935 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x936 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x937 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x9F8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x9FC 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x9FD 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x9FE 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x9FF 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xAC8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xACC 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xACD 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xACE 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xACF 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xBA0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xBA4 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xBA5 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xBA6 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xBA7 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xC80 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xC84 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xC85 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xC86 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xC87 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xD68 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xD6C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xD6D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xD6E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xD6F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xE58 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xE5C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xE5D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xE5E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xE5F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xF50 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xF54 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xF55 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xF56 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xF57 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x1050 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1054 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1055 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1056 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1057 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x1158 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x115C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x115D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x115E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x115F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x78 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x7C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x7D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x7E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x7F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x1268 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x126C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x126D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x126E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x126F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x1380 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1384 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1385 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1386 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[31]-CHANNEL[30]-CHANNEL[29]-CHANNEL[28]-CHANNEL[27]-CHANNEL[26]-CHANNEL[25]-CHANNEL[24]-CHANNEL[23]-CHANNEL[22]-CHANNEL[21]-CHANNEL[20]-CHANNEL[19]-CHANNEL[18]-CHANNEL[17]-CHANNEL[16]-CHANNEL[15]-CHANNEL[14]-CHANNEL[13]-CHANNEL[12]-CHANNEL[11]-CHANNEL[10]-CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1387 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xB0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xB4 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xB5 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xB6 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xB7 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0xF0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0xF4 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0xF5 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0xF6 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0xF7 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x138 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x13C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x13D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x13E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x13F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x188 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x18C 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x18D 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x18E 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x18F 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x1E0 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x1E4 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x1E5 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x1E6 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x1E7 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x240 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x244 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x245 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x246 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x247 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHANNEL Channel n Control 0x2A8 32 read-write n 0x0 0x0 EDGSEL Edge Detection Selection 10 2 EDGSELSelect NO_EVT_OUTPUT No event output when using the resynchronized or synchronous path 0 RISING_EDGE Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path 1 FALLING_EDGE Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path 2 BOTH_EDGES Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path 3 EVGEN Event Generator Selection 0 7 ONDEMAND Generic Clock On Demand 15 1 PATH Path Selection 8 2 PATHSelect SYNCHRONOUS Synchronous path 0 RESYNCHRONIZED Resynchronized path 1 ASYNCHRONOUS Asynchronous path 2 RUNSTDBY Run in standby 14 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENCLR Channel n Interrupt Enable Clear 0x2AC 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTENSET Channel n Interrupt Enable Set 0x2AD 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHINTFLAG Channel n Interrupt Flag Status and Clear 0x2AE 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHANNEL[9]-CHANNEL[8]-CHANNEL[7]-CHANNEL[6]-CHANNEL[5]-CHANNEL[4]-CHANNEL[3]-CHANNEL[2]-CHANNEL[1]-CHANNEL[0]-CHSTATUS Channel n Status 0x2AF 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CHINTENCLR Channel n Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Disable 1 1 OVR Channel Overrun Interrupt Disable 0 1 CHINTENSET Channel n Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EVD Channel Event Detected Interrupt Enable 1 1 OVR Channel Overrun Interrupt Enable 0 1 CHINTFLAG Channel n Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EVD Channel Event Detected 1 1 OVR Channel Overrun 0 1 CHSTATUS Channel n Status 0x7 8 read-only n 0x0 0x0 BUSYCH Busy Channel 1 1 RDYUSR Ready User 0 1 CTRLA Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 INTPEND Channel Pending Interrupt 0x10 16 read-write n 0x0 0x0 BUSY Busy 15 1 EVD Channel Event Detected 9 1 ID Channel ID 0 4 OVR Channel Overrun 8 1 READY Ready 14 1 INTSTATUS Interrupt Status 0x14 32 read-only n 0x0 0x0 CHINT0 Channel 0 Pending Interrupt 0 1 CHINT1 Channel 1 Pending Interrupt 1 1 CHINT10 Channel 10 Pending Interrupt 10 1 CHINT11 Channel 11 Pending Interrupt 11 1 CHINT2 Channel 2 Pending Interrupt 2 1 CHINT3 Channel 3 Pending Interrupt 3 1 CHINT4 Channel 4 Pending Interrupt 4 1 CHINT5 Channel 5 Pending Interrupt 5 1 CHINT6 Channel 6 Pending Interrupt 6 1 CHINT7 Channel 7 Pending Interrupt 7 1 CHINT8 Channel 8 Pending Interrupt 8 1 CHINT9 Channel 9 Pending Interrupt 9 1 PRICTRL Priority Control 0x8 8 read-write n 0x0 0x0 PRI Channel Priority Number 0 4 RREN Round-Robin Scheduling Enable 7 1 READYUSR Ready Users 0x1C 32 read-only n 0x0 0x0 READYUSR0 Ready User for Channel 0 0 1 READYUSR1 Ready User for Channel 1 1 1 READYUSR10 Ready User for Channel 10 10 1 READYUSR11 Ready User for Channel 11 11 1 READYUSR2 Ready User for Channel 2 2 1 READYUSR3 Ready User for Channel 3 3 1 READYUSR4 Ready User for Channel 4 4 1 READYUSR5 Ready User for Channel 5 5 1 READYUSR6 Ready User for Channel 6 6 1 READYUSR7 Ready User for Channel 7 7 1 READYUSR8 Ready User for Channel 8 8 1 READYUSR9 Ready User for Channel 9 9 1 SWEVT Software Event 0x4 32 write-only n 0x0 0x0 CHANNEL0 Channel 0 Software Selection 0 1 CHANNEL1 Channel 1 Software Selection 1 1 CHANNEL10 Channel 10 Software Selection 10 1 CHANNEL11 Channel 11 Software Selection 11 1 CHANNEL12 Channel 12 Software Selection 12 1 CHANNEL13 Channel 13 Software Selection 13 1 CHANNEL14 Channel 14 Software Selection 14 1 CHANNEL15 Channel 15 Software Selection 15 1 CHANNEL16 Channel 16 Software Selection 16 1 CHANNEL17 Channel 17 Software Selection 17 1 CHANNEL18 Channel 18 Software Selection 18 1 CHANNEL19 Channel 19 Software Selection 19 1 CHANNEL2 Channel 2 Software Selection 2 1 CHANNEL20 Channel 20 Software Selection 20 1 CHANNEL21 Channel 21 Software Selection 21 1 CHANNEL22 Channel 22 Software Selection 22 1 CHANNEL23 Channel 23 Software Selection 23 1 CHANNEL24 Channel 24 Software Selection 24 1 CHANNEL25 Channel 25 Software Selection 25 1 CHANNEL26 Channel 26 Software Selection 26 1 CHANNEL27 Channel 27 Software Selection 27 1 CHANNEL28 Channel 28 Software Selection 28 1 CHANNEL29 Channel 29 Software Selection 29 1 CHANNEL3 Channel 3 Software Selection 3 1 CHANNEL30 Channel 30 Software Selection 30 1 CHANNEL31 Channel 31 Software Selection 31 1 CHANNEL4 Channel 4 Software Selection 4 1 CHANNEL5 Channel 5 Software Selection 5 1 CHANNEL6 Channel 6 Software Selection 6 1 CHANNEL7 Channel 7 Software Selection 7 1 CHANNEL8 Channel 8 Software Selection 8 1 CHANNEL9 Channel 9 Software Selection 9 1 USER0 User Multiplexer n 0x120 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER1 User Multiplexer n 0x124 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER10 User Multiplexer n 0x148 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER11 User Multiplexer n 0x14C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER12 User Multiplexer n 0x150 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER13 User Multiplexer n 0x154 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER14 User Multiplexer n 0x158 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER15 User Multiplexer n 0x15C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER16 User Multiplexer n 0x160 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER17 User Multiplexer n 0x164 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER18 User Multiplexer n 0x168 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER19 User Multiplexer n 0x16C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER2 User Multiplexer n 0x128 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER20 User Multiplexer n 0x170 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER21 User Multiplexer n 0x174 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER22 User Multiplexer n 0x178 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER23 User Multiplexer n 0x17C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER24 User Multiplexer n 0x180 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER25 User Multiplexer n 0x184 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER26 User Multiplexer n 0x188 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER27 User Multiplexer n 0x18C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER28 User Multiplexer n 0x190 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER29 User Multiplexer n 0x194 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER3 User Multiplexer n 0x12C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER30 User Multiplexer n 0x198 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER31 User Multiplexer n 0x19C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER32 User Multiplexer n 0x1A0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER33 User Multiplexer n 0x1A4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER34 User Multiplexer n 0x1A8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER35 User Multiplexer n 0x1AC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER36 User Multiplexer n 0x1B0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER37 User Multiplexer n 0x1B4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER38 User Multiplexer n 0x1B8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER39 User Multiplexer n 0x1BC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER4 User Multiplexer n 0x130 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER40 User Multiplexer n 0x1C0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER41 User Multiplexer n 0x1C4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER42 User Multiplexer n 0x1C8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER43 User Multiplexer n 0x1CC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER44 User Multiplexer n 0x1D0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER45 User Multiplexer n 0x1D4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER46 User Multiplexer n 0x1D8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER47 User Multiplexer n 0x1DC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER48 User Multiplexer n 0x1E0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER49 User Multiplexer n 0x1E4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER5 User Multiplexer n 0x134 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER50 User Multiplexer n 0x1E8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER51 User Multiplexer n 0x1EC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER52 User Multiplexer n 0x1F0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER53 User Multiplexer n 0x1F4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER54 User Multiplexer n 0x1F8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER55 User Multiplexer n 0x1FC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER56 User Multiplexer n 0x200 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER57 User Multiplexer n 0x204 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER58 User Multiplexer n 0x208 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER59 User Multiplexer n 0x20C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER6 User Multiplexer n 0x138 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER60 User Multiplexer n 0x210 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER61 User Multiplexer n 0x214 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER62 User Multiplexer n 0x218 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER63 User Multiplexer n 0x21C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER64 User Multiplexer n 0x220 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER65 User Multiplexer n 0x224 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER66 User Multiplexer n 0x228 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER7 User Multiplexer n 0x13C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER8 User Multiplexer n 0x140 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER9 User Multiplexer n 0x144 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[0] User Multiplexer n 0x240 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[10] User Multiplexer n 0xE5C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[11] User Multiplexer n 0xFA8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[12] User Multiplexer n 0x10F8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[13] User Multiplexer n 0x124C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[14] User Multiplexer n 0x13A4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[15] User Multiplexer n 0x1500 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[16] User Multiplexer n 0x1660 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[17] User Multiplexer n 0x17C4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[18] User Multiplexer n 0x192C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[19] User Multiplexer n 0x1A98 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[1] User Multiplexer n 0x364 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[20] User Multiplexer n 0x1C08 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[21] User Multiplexer n 0x1D7C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[22] User Multiplexer n 0x1EF4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[23] User Multiplexer n 0x2070 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[24] User Multiplexer n 0x21F0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[25] User Multiplexer n 0x2374 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[26] User Multiplexer n 0x24FC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[27] User Multiplexer n 0x2688 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[28] User Multiplexer n 0x2818 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[29] User Multiplexer n 0x29AC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[2] User Multiplexer n 0x48C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[30] User Multiplexer n 0x2B44 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[31] User Multiplexer n 0x2CE0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[32] User Multiplexer n 0x2E80 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[33] User Multiplexer n 0x3024 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[34] User Multiplexer n 0x31CC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[35] User Multiplexer n 0x3378 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[36] User Multiplexer n 0x3528 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[37] User Multiplexer n 0x36DC 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[38] User Multiplexer n 0x3894 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[39] User Multiplexer n 0x3A50 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[3] User Multiplexer n 0x5B8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[40] User Multiplexer n 0x3C10 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[41] User Multiplexer n 0x3DD4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[42] User Multiplexer n 0x3F9C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[43] User Multiplexer n 0x4168 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[44] User Multiplexer n 0x4338 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[45] User Multiplexer n 0x450C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[46] User Multiplexer n 0x46E4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[47] User Multiplexer n 0x48C0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[48] User Multiplexer n 0x4AA0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[49] User Multiplexer n 0x4C84 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[4] User Multiplexer n 0x6E8 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[50] User Multiplexer n 0x4E6C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[51] User Multiplexer n 0x5058 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[52] User Multiplexer n 0x5248 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[53] User Multiplexer n 0x543C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[54] User Multiplexer n 0x5634 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[55] User Multiplexer n 0x5830 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[56] User Multiplexer n 0x5A30 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[57] User Multiplexer n 0x5C34 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[58] User Multiplexer n 0x5E3C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[59] User Multiplexer n 0x6048 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[5] User Multiplexer n 0x81C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[60] User Multiplexer n 0x6258 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[61] User Multiplexer n 0x646C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[62] User Multiplexer n 0x6684 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[63] User Multiplexer n 0x68A0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[64] User Multiplexer n 0x6AC0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[65] User Multiplexer n 0x6CE4 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[66] User Multiplexer n 0x6F0C 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[6] User Multiplexer n 0x954 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[7] User Multiplexer n 0xA90 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[8] User Multiplexer n 0xBD0 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 USER[9] User Multiplexer n 0xD14 32 read-write n 0x0 0x0 CHANNEL Channel Event Selection 0 6 FPU Floating Point Unit FPU 0x0 0x0 0x18 registers n FPCAR Floating-Point Context Address Register 0x8 32 read-write n 0x0 0x0 ADDRESS Address for FP registers in exception stack frame 3 29 FPCCR Floating-Point Context Control Register 0x4 32 read-write n 0x0 0x0 ASPEN 31 1 BFRDY 6 1 HFRDY 4 1 LSPACT 0 1 LSPEN 30 1 MMRDY 5 1 MONRDY 8 1 THREAD 3 1 USER 1 1 FPDSCR Floating-Point Default Status Control Register 0xC 32 read-write n 0x0 0x0 AHP Default value for FPSCR.AHP 26 1 DN Default value for FPSCR.DN 25 1 FZ Default value for FPSCR.FZ 24 1 RMODE Default value for FPSCR.RMODE 22 2 RMODESelect RN Round to Nearest 0 RP Round towards Positive Infinity 1 RM Round towards Negative Infinity 2 RZ Round towards Zero 3 MVFR0 Media and FP Feature Register 0 0x10 32 read-only n 0x0 0x0 A_SIMD_registers 0 4 Divide 16 4 Double_precision 8 4 FP_excep_trapping 12 4 FP_rounding_modes 28 4 Short_vectors 24 4 Single_precision 4 4 Square_root 20 4 MVFR1 Media and FP Feature Register 1 0x14 32 read-only n 0x0 0x0 D_NaN_mode 4 4 FP_fused_MAC 28 4 FP_HPFP 24 4 FtZ_mode 0 4 FREQM Frequency Meter FREQM 0x0 0x0 0x14 registers n FREQM 28 CFGA Config A register 0x2 16 read-write n 0x0 0x0 REFNUM Number of Reference Clock Cycles 0 8 CTRLA Control A Register 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 CTRLB Control B Register 0x1 8 write-only n 0x0 0x0 START Start Measurement 0 1 INTENCLR Interrupt Enable Clear Register 0x8 8 read-write n 0x0 0x0 DONE Measurement Done Interrupt Enable 0 1 INTENSET Interrupt Enable Set Register 0x9 8 read-write n 0x0 0x0 DONE Measurement Done Interrupt Enable 0 1 INTFLAG Interrupt Flag Register 0xA 8 read-write n 0x0 0x0 DONE Measurement Done 0 1 STATUS Status Register 0xB 8 read-write n 0x0 0x0 BUSY FREQM Status 0 1 OVF Sticky Count Value Overflow 1 1 SYNCBUSY Synchronization Busy Register 0xC 32 read-only n 0x0 0x0 ENABLE Enable 1 1 SWRST Software Reset 0 1 VALUE Count Value Register 0x10 32 read-only n 0x0 0x0 VALUE Measurement Value 0 24 GCLK Generic Clock Generator GCLK 0x0 0x0 0x1A0 registers n CTRLA Control 0x0 8 read-write n 0x0 0x0 SWRST Software Reset 0 1 GENCTRL0 Generic Clock Generator Control 0x20 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL1 Generic Clock Generator Control 0x24 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL10 Generic Clock Generator Control 0x48 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL11 Generic Clock Generator Control 0x4C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL2 Generic Clock Generator Control 0x28 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL3 Generic Clock Generator Control 0x2C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL4 Generic Clock Generator Control 0x30 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL5 Generic Clock Generator Control 0x34 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL6 Generic Clock Generator Control 0x38 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL7 Generic Clock Generator Control 0x3C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL8 Generic Clock Generator Control 0x40 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL9 Generic Clock Generator Control 0x44 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0x0 DIV2 Divide input by 2^(divider factor+ 1) 0x1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[0] Generic Clock Generator Control 0x40 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[10] Generic Clock Generator Control 0x25C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[11] Generic Clock Generator Control 0x2A8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[1] Generic Clock Generator Control 0x64 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[2] Generic Clock Generator Control 0x8C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[3] Generic Clock Generator Control 0xB8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[4] Generic Clock Generator Control 0xE8 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[5] Generic Clock Generator Control 0x11C 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[6] Generic Clock Generator Control 0x154 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[7] Generic Clock Generator Control 0x190 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[8] Generic Clock Generator Control 0x1D0 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 GENCTRL[9] Generic Clock Generator Control 0x214 32 read-write n 0x0 0x0 DIV Division Factor 16 16 DIVSEL Divide Selection 12 1 DIVSELSelect DIV1 Divide input directly by divider factor 0 DIV2 Divide input by 2^(divider factor+ 1) 1 GENEN Generic Clock Generator Enable 8 1 IDC Improve Duty Cycle 9 1 OE Output Enable 11 1 OOV Output Off Value 10 1 RUNSTDBY Run in Standby 13 1 SRC Source Select 0 4 SRCSelect XOSC0 XOSC0 oscillator output 0 XOSC1 XOSC1 oscillator output 1 GCLKIN Generator input pad 2 GCLKGEN1 Generic clock generator 1 output 3 OSCULP32K OSCULP32K oscillator output 4 XOSC32K XOSC32K oscillator output 5 DFLL DFLL output 6 DPLL0 DPLL0 output 7 DPLL1 DPLL1 output 8 PCHCTRL0 Peripheral Clock Control 0x80 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL1 Peripheral Clock Control 0x84 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL10 Peripheral Clock Control 0xA8 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL11 Peripheral Clock Control 0xAC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL12 Peripheral Clock Control 0xB0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL13 Peripheral Clock Control 0xB4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL14 Peripheral Clock Control 0xB8 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL15 Peripheral Clock Control 0xBC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL16 Peripheral Clock Control 0xC0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL17 Peripheral Clock Control 0xC4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL18 Peripheral Clock Control 0xC8 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL19 Peripheral Clock Control 0xCC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL2 Peripheral Clock Control 0x88 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL20 Peripheral Clock Control 0xD0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL21 Peripheral Clock Control 0xD4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL22 Peripheral Clock Control 0xD8 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL23 Peripheral Clock Control 0xDC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL24 Peripheral Clock Control 0xE0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL25 Peripheral Clock Control 0xE4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL26 Peripheral Clock Control 0xE8 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL27 Peripheral Clock Control 0xEC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL28 Peripheral Clock Control 0xF0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL29 Peripheral Clock Control 0xF4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL3 Peripheral Clock Control 0x8C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL30 Peripheral Clock Control 0xF8 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL31 Peripheral Clock Control 0xFC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL32 Peripheral Clock Control 0x100 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL33 Peripheral Clock Control 0x104 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL34 Peripheral Clock Control 0x108 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL35 Peripheral Clock Control 0x10C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL36 Peripheral Clock Control 0x110 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL37 Peripheral Clock Control 0x114 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL38 Peripheral Clock Control 0x118 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL39 Peripheral Clock Control 0x11C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL4 Peripheral Clock Control 0x90 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL40 Peripheral Clock Control 0x120 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL41 Peripheral Clock Control 0x124 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL42 Peripheral Clock Control 0x128 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL43 Peripheral Clock Control 0x12C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL44 Peripheral Clock Control 0x130 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL45 Peripheral Clock Control 0x134 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL46 Peripheral Clock Control 0x138 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL47 Peripheral Clock Control 0x13C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL5 Peripheral Clock Control 0x94 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL6 Peripheral Clock Control 0x98 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL7 Peripheral Clock Control 0x9C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL8 Peripheral Clock Control 0xA0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL9 Peripheral Clock Control 0xA4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0x0 GCLK1 Generic clock generator 1 0x1 GCLK2 Generic clock generator 2 0x2 GCLK3 Generic clock generator 3 0x3 GCLK4 Generic clock generator 4 0x4 GCLK5 Generic clock generator 5 0x5 GCLK6 Generic clock generator 6 0x6 GCLK7 Generic clock generator 7 0x7 GCLK8 Generic clock generator 8 0x8 GCLK9 Generic clock generator 9 0x9 GCLK10 Generic clock generator 10 0xA GCLK11 Generic clock generator 11 0xB WRTLOCK Write Lock 7 1 PCHCTRL[0] Peripheral Clock Control 0x100 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[10] Peripheral Clock Control 0x6DC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[11] Peripheral Clock Control 0x788 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[12] Peripheral Clock Control 0x838 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[13] Peripheral Clock Control 0x8EC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[14] Peripheral Clock Control 0x9A4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[15] Peripheral Clock Control 0xA60 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[16] Peripheral Clock Control 0xB20 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[17] Peripheral Clock Control 0xBE4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[18] Peripheral Clock Control 0xCAC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[19] Peripheral Clock Control 0xD78 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[1] Peripheral Clock Control 0x184 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[20] Peripheral Clock Control 0xE48 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[21] Peripheral Clock Control 0xF1C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[22] Peripheral Clock Control 0xFF4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[23] Peripheral Clock Control 0x10D0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[24] Peripheral Clock Control 0x11B0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[25] Peripheral Clock Control 0x1294 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[26] Peripheral Clock Control 0x137C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[27] Peripheral Clock Control 0x1468 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[28] Peripheral Clock Control 0x1558 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[29] Peripheral Clock Control 0x164C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[2] Peripheral Clock Control 0x20C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[30] Peripheral Clock Control 0x1744 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[31] Peripheral Clock Control 0x1840 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[32] Peripheral Clock Control 0x1940 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[33] Peripheral Clock Control 0x1A44 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[34] Peripheral Clock Control 0x1B4C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[35] Peripheral Clock Control 0x1C58 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[36] Peripheral Clock Control 0x1D68 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[37] Peripheral Clock Control 0x1E7C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[38] Peripheral Clock Control 0x1F94 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[39] Peripheral Clock Control 0x20B0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[3] Peripheral Clock Control 0x298 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[40] Peripheral Clock Control 0x21D0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[41] Peripheral Clock Control 0x22F4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[42] Peripheral Clock Control 0x241C 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[43] Peripheral Clock Control 0x2548 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[44] Peripheral Clock Control 0x2678 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[45] Peripheral Clock Control 0x27AC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[46] Peripheral Clock Control 0x28E4 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[47] Peripheral Clock Control 0x2A20 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[4] Peripheral Clock Control 0x328 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[5] Peripheral Clock Control 0x3BC 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[6] Peripheral Clock Control 0x454 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[7] Peripheral Clock Control 0x4F0 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[8] Peripheral Clock Control 0x590 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 PCHCTRL[9] Peripheral Clock Control 0x634 32 read-write n 0x0 0x0 CHEN Channel Enable 6 1 GEN Generic Clock Generator 0 4 GENSelect GCLK0 Generic clock generator 0 0 GCLK1 Generic clock generator 1 1 GCLK10 Generic clock generator 10 10 GCLK11 Generic clock generator 11 11 GCLK2 Generic clock generator 2 2 GCLK3 Generic clock generator 3 3 GCLK4 Generic clock generator 4 4 GCLK5 Generic clock generator 5 5 GCLK6 Generic clock generator 6 6 GCLK7 Generic clock generator 7 7 GCLK8 Generic clock generator 8 8 GCLK9 Generic clock generator 9 9 WRTLOCK Write Lock 7 1 SYNCBUSY Synchronization Busy 0x4 32 read-only n 0x0 0x0 GENCTRL Generic Clock Generator Control n Synchronization Busy bits 2 12 GENCTRLSelect GCLK0 Generic clock generator 0 1 GCLK10 Generic clock generator 10 1024 GCLK7 Generic clock generator 7 128 GCLK4 Generic clock generator 4 16 GCLK1 Generic clock generator 1 2 GCLK11 Generic clock generator 11 2048 GCLK8 Generic clock generator 8 256 GCLK5 Generic clock generator 5 32 GCLK2 Generic clock generator 2 4 GCLK9 Generic clock generator 9 512 GCLK6 Generic clock generator 6 64 GCLK3 Generic clock generator 3 8 SWRST Software Reset Synchroniation Busy bit 0 1 GMAC Ethernet MAC GMAC 0x0 0x0 0x280 registers n GMAC 84 AE Alignment Errors Register 0x19C 32 read-only n 0x0 0x0 AER Alignment Errors 0 10 BCFR Broadcast Frames Received Register 0x15C 32 read-only n 0x0 0x0 BFRX Broadcast Frames Received without Error 0 32 BCFT Broadcast Frames Transmitted Register 0x10C 32 read-only n 0x0 0x0 BFTX Broadcast Frames Transmitted without Error 0 32 BFR64 64 Byte Frames Received Register 0x168 32 read-only n 0x0 0x0 NFRX 64 Byte Frames Received without Error 0 32 BFT64 64 Byte Frames Transmitted Register 0x118 32 read-only n 0x0 0x0 NFTX 64 Byte Frames Transmitted without Error 0 32 CSE Carrier Sense Errors Register 0x14C 32 read-only n 0x0 0x0 CSR Carrier Sense Error 0 10 DCFGR DMA Configuration Register 0x10 32 read-write n 0x0 0x0 DDRP DMA Discard Receive Packets 24 1 DRBS DMA Receive Buffer Size 16 8 ESMA Endian Swap Mode Enable for Management Descriptor Accesses 6 1 ESPA Endian Swap Mode Enable for Packet Data Accesses 7 1 FBLDO Fixed Burst Length for DMA Data Operations: 0 5 RXBMS Receiver Packet Buffer Memory Size Select 8 2 TXCOEN Transmitter Checksum Generation Offload Enable 11 1 TXPBMS Transmitter Packet Buffer Memory Size Select 10 1 DTF Deferred Transmission Frames Register 0x148 32 read-only n 0x0 0x0 DEFT Deferred Transmission 0 18 EC Excessive Collisions Register 0x140 32 read-only n 0x0 0x0 XCOL Excessive Collisions 0 10 EFRN PTP Event Frame Received Nanoseconds 0x1EC 32 read-only n 0x0 0x0 RUD Register Update 0 30 EFRSH PTP Event Frame Received Seconds High Register 0xEC 32 read-only n 0x0 0x0 RUD Register Update 0 16 EFRSL PTP Event Frame Received Seconds Low Register 0x1E8 32 read-only n 0x0 0x0 RUD Register Update 0 32 EFTN PTP Event Frame Transmitted Nanoseconds 0x1E4 32 read-only n 0x0 0x0 RUD Register Update 0 30 EFTSH PTP Event Frame Transmitted Seconds High Register 0xE8 32 read-only n 0x0 0x0 RUD Register Update 0 16 EFTSL PTP Event Frame Transmitted Seconds Low Register 0x1E0 32 read-only n 0x0 0x0 RUD Register Update 0 32 FCSE Frame Check Sequence Errors Register 0x190 32 read-only n 0x0 0x0 FCKR Frame Check Sequence Errors 0 10 FR Frames Received Register 0x158 32 read-only n 0x0 0x0 FRX Frames Received without Error 0 32 FT Frames Transmitted Register 0x108 32 read-only n 0x0 0x0 FTX Frames Transmitted without Error 0 32 GTBFT1518 Greater Than 1518 Byte Frames Transmitted Register 0x130 32 read-only n 0x0 0x0 NFTX Greater than 1518 Byte Frames Transmitted without Error 0 32 HRB Hash Register Bottom [31:0] 0x80 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 HRT Hash Register Top [63:32] 0x84 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 IDR Interrupt Disable Register 0x2C 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 EXINT External Interrupt 15 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TSUCMP Tsu timer comparison 29 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 IER Interrupt Enable Register 0x28 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 EXINT External Interrupt 15 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TSUCMP Tsu timer comparison 29 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 IHCE IP Header Checksum Errors Register 0x1A8 32 read-only n 0x0 0x0 HCKER IP Header Checksum Errors 0 8 IMR Interrupt Mask Register 0x30 32 read-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 EXINT External Interrupt 15 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TSUCMP Tsu timer comparison 29 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On Lan 28 1 IPGS IPG Stretch Register 0xBC 32 read-write n 0x0 0x0 FL Frame Length 0 16 ISR Interrupt Status Register 0x24 32 read-write n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TSUCMP Tsu timer comparison 29 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 JR Jabbers Received Register 0x18C 32 read-only n 0x0 0x0 JRX Jabbers Received 0 10 LC Late Collisions Register 0x144 32 read-only n 0x0 0x0 LCOL Late Collisions 0 10 LFFE Length Field Frame Errors Register 0x194 32 read-only n 0x0 0x0 LFER Length Field Frame Errors 0 10 MAN PHY Maintenance Register 0x34 32 read-write n 0x0 0x0 CLTTO Clause 22 Operation 30 1 DATA PHY Data 0 16 OP Operation 28 2 PHYA PHY Address 23 5 REGA Register Address 18 5 WTN Write Ten 16 2 WZO Write ZERO 31 1 MCF Multiple Collision Frames Register 0x13C 32 read-only n 0x0 0x0 MCOL Multiple Collision 0 18 MFR Multicast Frames Received Register 0x160 32 read-only n 0x0 0x0 MFRX Multicast Frames Received without Error 0 32 MFT Multicast Frames Transmitted Register 0x110 32 read-only n 0x0 0x0 MFTX Multicast Frames Transmitted without Error 0 32 NCFGR Network Configuration Register 0x4 32 read-write n 0x0 0x0 CAF Copy All Frames 4 1 CLK MDC CLock Division 18 3 DBW Data Bus Width 21 2 DCPF Disable Copy of Pause Frames 23 1 DNVLAN Discard Non-VLAN FRAMES 2 1 EFRHD Enable Frames Received in Half Duplex 25 1 FD Full Duplex 1 1 IPGSEN IP Stretch Enable 28 1 IRXER Ignore IPG GRXER 30 1 IRXFCS Ignore RX FCS 26 1 JFRAME Jumbo Frame Size 3 1 LFERD Length Field Error Frame Discard 16 1 MAXFS 1536 Maximum Frame Size 8 1 MTIHEN Multicast Hash Enable 6 1 NBC No Broadcast 5 1 PEN Pause Enable 13 1 RFCS Remove FCS 17 1 RTY Retry Test 12 1 RXBP Receive Bad Preamble 29 1 RXBUFO Receive Buffer Offset 14 2 RXCOEN Receive Checksum Offload Enable 24 1 SPD Speed 0 1 UNIHEN Unicast Hash Enable 7 1 NCR Network Control Register 0x0 32 read-write n 0x0 0x0 BP Back pressure 8 1 CLRSTAT Clear Statistics Registers 5 1 ENPBPR Enable PFC Priority-based Pause Reception 16 1 FNP Flush Next Packet 18 1 INCSTAT Increment Statistics Registers 6 1 LBL Loop Back Local 1 1 LPI Low Power Idle Enable 19 1 MPE Management Port Enable 4 1 RXEN Receive Enable 2 1 SRTSM Store Receive Time Stamp to Memory 15 1 THALT Transmit Halt 10 1 TSTART Start Transmission 9 1 TXEN Transmit Enable 3 1 TXPBPF Transmit PFC Priority-based Pause Frame 17 1 TXPF Transmit Pause Frame 11 1 TXZQPF Transmit Zero Quantum Pause Frame 12 1 WESTAT Write Enable for Statistics Registers 7 1 NSC Tsu timer comparison nanoseconds Register 0xDC 32 read-write n 0x0 0x0 NANOSEC 1588 Timer Nanosecond comparison value 0 21 NSR Network Status Register 0x8 32 read-only n 0x0 0x0 IDLE PHY Management Logic Idle 2 1 MDIO MDIO Input Status 1 1 OFR Oversize Frames Received Register 0x188 32 read-only n 0x0 0x0 OFRX Oversized Frames Received 0 10 ORHI Octets Received [47:32] Received 0x154 32 read-only n 0x0 0x0 RXO Received Octets 0 16 ORLO Octets Received [31:0] Received 0x150 32 read-only n 0x0 0x0 RXO Received Octets 0 32 OTHI Octets Transmitted [47:32] Register 0x104 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 16 OTLO Octets Transmitted [31:0] Register 0x100 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 32 PEFRN PTP Peer Event Frame Received Nanoseconds 0x1FC 32 read-only n 0x0 0x0 RUD Register Update 0 30 PEFRSH PTP Peer Event Frame Received Seconds High Register 0xF4 32 read-only n 0x0 0x0 RUD Register Update 0 16 PEFRSL PTP Peer Event Frame Received Seconds Low Register 0x1F8 32 read-only n 0x0 0x0 RUD Register Update 0 32 PEFTN PTP Peer Event Frame Transmitted Nanoseconds 0x1F4 32 read-only n 0x0 0x0 RUD Register Update 0 30 PEFTSH PTP Peer Event Frame Transmitted Seconds High Register 0xF0 32 read-only n 0x0 0x0 RUD Register Update 0 16 PEFTSL PTP Peer Event Frame Transmitted Seconds Low Register 0x1F0 32 read-only n 0x0 0x0 RUD Register Update 0 32 PFR Pause Frames Received Register 0x164 32 read-only n 0x0 0x0 PFRX Pause Frames Received Register 0 16 PFT Pause Frames Transmitted Register 0x114 32 read-only n 0x0 0x0 PFTX Pause Frames Transmitted Register 0 16 RBQB Receive Buffer Queue Base Address 0x18 32 read-write n 0x0 0x0 ADDR Receive Buffer Queue Base Address 2 30 RJFML RX Jumbo Frame Max Length Register 0x48 32 read-write n 0x0 0x0 FML Frame Max Length 0 14 RLPITI Receive LPI Time Register 0x274 32 read-only n 0x0 0x0 RLPITI Increment once over 16 ahb clock when LPI indication bit 20 is set in rx mode 0 24 RLPITR Receive LPI transition Register 0x270 32 read-only n 0x0 0x0 RLPITR Count number of times transition from rx normal idle to low power idle 0 16 ROE Receive Overrun Register 0x1A4 32 read-only n 0x0 0x0 RXOVR Receive Overruns 0 10 RPQ Received Pause Quantum Register 0x38 32 read-only n 0x0 0x0 RPQ Received Pause Quantum 0 16 RPSF RX partial store and forward Register 0x44 32 read-write n 0x0 0x0 ENRXP Enable RX partial store and forward operation 31 1 RPB1ADR RX packet buffer address 0 10 RRE Receive Resource Errors Register 0x1A0 32 read-only n 0x0 0x0 RXRER Receive Resource Errors 0 18 RSE Receive Symbol Errors Register 0x198 32 read-only n 0x0 0x0 RXSE Receive Symbol Errors 0 10 RSR Receive Status Register 0x20 32 read-write n 0x0 0x0 BNA Buffer Not Available 0 1 HNO HRESP Not OK 3 1 REC Frame Received 1 1 RXOVR Receive Overrun 2 1 SAB Specific Address Bottom [31:0] Register 0x0 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SAMB1 Specific Address 1 Mask Bottom [31:0] Register 0xC8 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 32 SAMT1 Specific Address 1 Mask Top [47:32] Register 0xCC 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 16 SAT Specific Address Top [47:32] Register 0x4 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA[0]-SAB Specific Address Bottom [31:0] Register 0x88 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA[0]-SAT Specific Address Top [47:32] Register 0x8C 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA[1]-SA[0]-SAB Specific Address Bottom [31:0] Register 0x118 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA[1]-SA[0]-SAT Specific Address Top [47:32] Register 0x11C 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA[2]-SA[1]-SA[0]-SAB Specific Address Bottom [31:0] Register 0x1B0 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA[2]-SA[1]-SA[0]-SAT Specific Address Top [47:32] Register 0x1B4 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA[3]-SA[2]-SA[1]-SA[0]-SAB Specific Address Bottom [31:0] Register 0x250 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA[3]-SA[2]-SA[1]-SA[0]-SAT Specific Address Top [47:32] Register 0x254 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SCF Single Collision Frames Register 0x138 32 read-only n 0x0 0x0 SCOL Single Collision 0 18 SCH Tsu timer second comparison Register 0xE4 32 read-write n 0x0 0x0 SEC 1588 Timer Second comparison value 0 16 SCL Tsu timer second comparison Register 0xE0 32 read-write n 0x0 0x0 SEC 1588 Timer Second comparison value 0 32 SVLAN Stacked VLAN Register 0xC0 32 read-write n 0x0 0x0 ESVLAN Enable Stacked VLAN Processing Mode 31 1 VLAN_TYPE User Defined VLAN_TYPE Field 0 16 TA 1588 Timer Adjust Register 0x1D8 32 write-only n 0x0 0x0 ADJ Adjust 1588 Timer 31 1 ITDT Increment/Decrement 0 30 TBFR1023 512 to 1023 Byte Frames Received Register 0x178 32 read-only n 0x0 0x0 NFRX 512 to 1023 Byte Frames Received without Error 0 32 TBFR127 65 to 127 Byte Frames Received Register 0x16C 32 read-only n 0x0 0x0 NFRX 65 to 127 Byte Frames Received without Error 0 32 TBFR1518 1024 to 1518 Byte Frames Received Register 0x17C 32 read-only n 0x0 0x0 NFRX 1024 to 1518 Byte Frames Received without Error 0 32 TBFR255 128 to 255 Byte Frames Received Register 0x170 32 read-only n 0x0 0x0 NFRX 128 to 255 Byte Frames Received without Error 0 32 TBFR511 256 to 511Byte Frames Received Register 0x174 32 read-only n 0x0 0x0 NFRX 256 to 511 Byte Frames Received without Error 0 32 TBFT1023 512 to 1023 Byte Frames Transmitted Register 0x128 32 read-only n 0x0 0x0 NFTX 512 to 1023 Byte Frames Transmitted without Error 0 32 TBFT127 65 to 127 Byte Frames Transmitted Register 0x11C 32 read-only n 0x0 0x0 NFTX 65 to 127 Byte Frames Transmitted without Error 0 32 TBFT1518 1024 to 1518 Byte Frames Transmitted Register 0x12C 32 read-only n 0x0 0x0 NFTX 1024 to 1518 Byte Frames Transmitted without Error 0 32 TBFT255 128 to 255 Byte Frames Transmitted Register 0x120 32 read-only n 0x0 0x0 NFTX 128 to 255 Byte Frames Transmitted without Error 0 32 TBFT511 256 to 511 Byte Frames Transmitted Register 0x124 32 read-only n 0x0 0x0 NFTX 256 to 511 Byte Frames Transmitted without Error 0 32 TBQB Transmit Buffer Queue Base Address 0x1C 32 read-write n 0x0 0x0 ADDR Transmit Buffer Queue Base Address 2 30 TCE TCP Checksum Errors Register 0x1AC 32 read-only n 0x0 0x0 TCKER TCP Checksum Errors 0 8 TI 1588 Timer Increment Register 0x1DC 32 read-write n 0x0 0x0 ACNS Alternative Count Nanoseconds 8 8 CNS Count Nanoseconds 0 8 NIT Number of Increments 16 8 TIDM0 Type ID Match n Register 0xA8 32 read-write n 0x0 0x0 ENID Enable Copying of TID n Matched Frames 31 1 TID Type ID Match n 0 16 TIDM1 Type ID Match n Register 0xAC 32 read-write n 0x0 0x0 ENID Enable Copying of TID n Matched Frames 31 1 TID Type ID Match n 0 16 TIDM2 Type ID Match n Register 0xB0 32 read-write n 0x0 0x0 ENID Enable Copying of TID n Matched Frames 31 1 TID Type ID Match n 0 16 TIDM3 Type ID Match n Register 0xB4 32 read-write n 0x0 0x0 ENID Enable Copying of TID n Matched Frames 31 1 TID Type ID Match n 0 16 TIDM[0] Type ID Match Register 0x150 32 read-write n 0x0 0x0 TID Type ID Match 1 0 16 TIDM[1] Type ID Match Register 0x1FC 32 read-write n 0x0 0x0 TID Type ID Match 1 0 16 TIDM[2] Type ID Match Register 0x2AC 32 read-write n 0x0 0x0 TID Type ID Match 1 0 16 TIDM[3] Type ID Match Register 0x360 32 read-write n 0x0 0x0 TID Type ID Match 1 0 16 TISUBN 1588 Timer Increment [15:0] Sub-Nanoseconds Register 0x1BC 32 read-write n 0x0 0x0 LSBTIR Lower Significant Bits of Timer Increment 0 16 TLPITI Receive LPI Time Register 0x27C 32 read-only n 0x0 0x0 TLPITI Increment once over 16 ahb clock when LPI indication bit 20 is set in tx mode 0 24 TLPITR Receive LPI transition Register 0x278 32 read-only n 0x0 0x0 TLPITR Count number of times enable LPI tx bit 20 goes from low to high 0 16 TMXBFR 1519 to Maximum Byte Frames Received Register 0x180 32 read-only n 0x0 0x0 NFRX 1519 to Maximum Byte Frames Received without Error 0 32 TN 1588 Timer Nanoseconds Register 0x1D4 32 read-write n 0x0 0x0 TNS Timer Count in Nanoseconds 0 30 TPFCP Transmit PFC Pause Register 0xC4 32 read-write n 0x0 0x0 PEV Priority Enable Vector 0 8 PQ Pause Quantum 8 8 TPQ Transmit Pause Quantum Register 0x3C 32 read-write n 0x0 0x0 TPQ Transmit Pause Quantum 0 16 TPSF TX partial store and forward Register 0x40 32 read-write n 0x0 0x0 ENTXP Enable TX partial store and forward operation 31 1 TPB1ADR TX packet buffer address 0 10 TSH 1588 Timer Seconds High [15:0] Register 0x1C0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 16 TSL 1588 Timer Seconds [31:0] Register 0x1D0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 32 TSR Transmit Status Register 0x14 32 read-write n 0x0 0x0 COL Collision Occurred 1 1 HRESP HRESP Not OK 8 1 RLE Retry Limit Exceeded 2 1 TFC Transmit Frame Corruption Due to AHB Error 4 1 TXCOMP Transmit Complete 5 1 TXGO Transmit Go 3 1 UBR Used Bit Read 0 1 UND Transmit Underrun 6 1 TSSN 1588 Timer Sync Strobe Nanoseconds Register 0x1CC 32 read-write n 0x0 0x0 VTN Value Timer Nanoseconds Register Capture 0 30 TSSSL 1588 Timer Sync Strobe Seconds [31:0] Register 0x1C8 32 read-write n 0x0 0x0 VTS Value of Timer Seconds Register Capture 0 32 TUR Transmit Underruns Register 0x134 32 read-only n 0x0 0x0 TXUNR Transmit Underruns 0 10 UCE UDP Checksum Errors Register 0x1B0 32 read-only n 0x0 0x0 UCKER UDP Checksum Errors 0 8 UFR Undersize Frames Received Register 0x184 32 read-only n 0x0 0x0 UFRX Undersize Frames Received 0 10 UR User Register 0xC 32 read-write n 0x0 0x0 MII MII Mode 0 1 WOL Wake on LAN 0xB8 32 read-write n 0x0 0x0 ARP LAN ARP req 17 1 IP IP address 0 16 MAG Event enable 16 1 MTI WOL LAN multicast 19 1 SA1 WOL specific address reg 1 18 1 HMATRIX HSB Matrix HMATRIXB 0x0 0x0 0xB0 registers n HMATRIXB_PRS[0]-PRAS Priority A for Slave 0x80 32 read-write n 0x0 0x0 HMATRIXB_PRS[0]-PRBS Priority B for Slave 0x84 32 read-write n 0x0 0x0 HMATRIXB_PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x738 32 read-write n 0x0 0x0 HMATRIXB_PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x73C 32 read-write n 0x0 0x0 HMATRIXB_PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x810 32 read-write n 0x0 0x0 HMATRIXB_PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x814 32 read-write n 0x0 0x0 HMATRIXB_PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x8F0 32 read-write n 0x0 0x0 HMATRIXB_PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x8F4 32 read-write n 0x0 0x0 HMATRIXB_PRS[13]-PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x9D8 32 read-write n 0x0 0x0 HMATRIXB_PRS[13]-PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x9DC 32 read-write n 0x0 0x0 HMATRIXB_PRS[14]-PRS[13]-PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0xAC8 32 read-write n 0x0 0x0 HMATRIXB_PRS[14]-PRS[13]-PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0xACC 32 read-write n 0x0 0x0 HMATRIXB_PRS[15]-PRS[14]-PRS[13]-PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0xBC0 32 read-write n 0x0 0x0 HMATRIXB_PRS[15]-PRS[14]-PRS[13]-PRS[12]-PRS[11]-PRS[10]-PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0xBC4 32 read-write n 0x0 0x0 HMATRIXB_PRS[1]-PRS[0]-PRAS Priority A for Slave 0x108 32 read-write n 0x0 0x0 HMATRIXB_PRS[1]-PRS[0]-PRBS Priority B for Slave 0x10C 32 read-write n 0x0 0x0 HMATRIXB_PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x198 32 read-write n 0x0 0x0 HMATRIXB_PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x19C 32 read-write n 0x0 0x0 HMATRIXB_PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x230 32 read-write n 0x0 0x0 HMATRIXB_PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x234 32 read-write n 0x0 0x0 HMATRIXB_PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x2D0 32 read-write n 0x0 0x0 HMATRIXB_PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x2D4 32 read-write n 0x0 0x0 HMATRIXB_PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x378 32 read-write n 0x0 0x0 HMATRIXB_PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x37C 32 read-write n 0x0 0x0 HMATRIXB_PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x428 32 read-write n 0x0 0x0 HMATRIXB_PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x42C 32 read-write n 0x0 0x0 HMATRIXB_PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x4E0 32 read-write n 0x0 0x0 HMATRIXB_PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x4E4 32 read-write n 0x0 0x0 HMATRIXB_PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x5A0 32 read-write n 0x0 0x0 HMATRIXB_PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x5A4 32 read-write n 0x0 0x0 HMATRIXB_PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRAS Priority A for Slave 0x668 32 read-write n 0x0 0x0 HMATRIXB_PRS[9]-PRS[8]-PRS[7]-PRS[6]-PRS[5]-PRS[4]-PRS[3]-PRS[2]-PRS[1]-PRS[0]-PRBS Priority B for Slave 0x66C 32 read-write n 0x0 0x0 PRAS Priority A for Slave 0x0 32 read-write n 0x0 0x0 PRBS Priority B for Slave 0x4 32 read-write n 0x0 0x0 I2S Inter-IC Sound Interface I2S 0x0 0x0 0x38 registers n I2S 128 CLKCTRL0 Clock Unit n Control 0x4 32 read-write n 0x0 0x0 BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0x0 I2S I2S (1 Bit Delay) 0x1 FSINV Frame Sync Invert 9 1 FSOUTINV Frame Sync Output Invert 10 1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x0 FSPIN FSn input pin is used as Frame Sync n source 0x1 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x0 HALF Frame Sync Pulse is half a Frame wide 0x1 BIT Frame Sync Pulse is 1 Bit wide 0x2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 0x3 MCKDIV Master Clock Division Factor 16 6 MCKEN Master Clock Enable 14 1 MCKOUTDIV Master Clock Output Division Factor 24 6 MCKOUTINV Master Clock Output Invert 15 1 MCKSEL Master Clock Select 13 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0x0 MCKPIN MCKn input pin is used as Master Clock n source 0x1 NBSLOTS Number of Slots in Frame 2 3 SCKOUTINV Serial Clock Output Invert 12 1 SCKSEL Serial Clock Select 11 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0x0 SCKPIN SCKn input pin is used as Serial Clock n source 0x1 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0x0 16 16-bit Slot for Clock Unit n 0x1 24 24-bit Slot for Clock Unit n 0x2 32 32-bit Slot for Clock Unit n 0x3 CLKCTRL1 Clock Unit n Control 0x8 32 read-write n 0x0 0x0 BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0x0 I2S I2S (1 Bit Delay) 0x1 FSINV Frame Sync Invert 9 1 FSOUTINV Frame Sync Output Invert 10 1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0x0 FSPIN FSn input pin is used as Frame Sync n source 0x1 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0x0 HALF Frame Sync Pulse is half a Frame wide 0x1 BIT Frame Sync Pulse is 1 Bit wide 0x2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 0x3 MCKDIV Master Clock Division Factor 16 6 MCKEN Master Clock Enable 14 1 MCKOUTDIV Master Clock Output Division Factor 24 6 MCKOUTINV Master Clock Output Invert 15 1 MCKSEL Master Clock Select 13 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0x0 MCKPIN MCKn input pin is used as Master Clock n source 0x1 NBSLOTS Number of Slots in Frame 2 3 SCKOUTINV Serial Clock Output Invert 12 1 SCKSEL Serial Clock Select 11 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0x0 SCKPIN SCKn input pin is used as Serial Clock n source 0x1 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0x0 16 16-bit Slot for Clock Unit n 0x1 24 24-bit Slot for Clock Unit n 0x2 32 32-bit Slot for Clock Unit n 0x3 CLKCTRL[0] Clock Unit n Control 0x8 32 read-write n 0x0 0x0 BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0 I2S I2S (1 Bit Delay) 1 FSINV Frame Sync Invert 9 1 FSOUTINV Frame Sync Output Invert 10 1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0 FSPIN FSn input pin is used as Frame Sync n source 1 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0 HALF Frame Sync Pulse is half a Frame wide 1 BIT Frame Sync Pulse is 1 Bit wide 2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 3 MCKDIV Master Clock Division Factor 16 6 MCKEN Master Clock Enable 14 1 MCKOUTDIV Master Clock Output Division Factor 24 6 MCKOUTINV Master Clock Output Invert 15 1 MCKSEL Master Clock Select 13 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0 MCKPIN MCKn input pin is used as Master Clock n source 1 NBSLOTS Number of Slots in Frame 2 3 SCKOUTINV Serial Clock Output Invert 12 1 SCKSEL Serial Clock Select 11 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0 SCKPIN SCKn input pin is used as Serial Clock n source 1 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0 16 16-bit Slot for Clock Unit n 1 24 24-bit Slot for Clock Unit n 2 32 32-bit Slot for Clock Unit n 3 CLKCTRL[1] Clock Unit n Control 0x10 32 read-write n 0x0 0x0 BITDELAY Data Delay from Frame Sync 7 1 BITDELAYSelect LJ Left Justified (0 Bit Delay) 0 I2S I2S (1 Bit Delay) 1 FSINV Frame Sync Invert 9 1 FSOUTINV Frame Sync Output Invert 10 1 FSSEL Frame Sync Select 8 1 FSSELSelect SCKDIV Divided Serial Clock n is used as Frame Sync n source 0 FSPIN FSn input pin is used as Frame Sync n source 1 FSWIDTH Frame Sync Width 5 2 FSWIDTHSelect SLOT Frame Sync Pulse is 1 Slot wide (default for I2S protocol) 0 HALF Frame Sync Pulse is half a Frame wide 1 BIT Frame Sync Pulse is 1 Bit wide 2 BURST Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested 3 MCKDIV Master Clock Division Factor 16 6 MCKEN Master Clock Enable 14 1 MCKOUTDIV Master Clock Output Division Factor 24 6 MCKOUTINV Master Clock Output Invert 15 1 MCKSEL Master Clock Select 13 1 MCKSELSelect GCLK GCLK_I2S_n is used as Master Clock n source 0 MCKPIN MCKn input pin is used as Master Clock n source 1 NBSLOTS Number of Slots in Frame 2 3 SCKOUTINV Serial Clock Output Invert 12 1 SCKSEL Serial Clock Select 11 1 SCKSELSelect MCKDIV Divided Master Clock n is used as Serial Clock n source 0 SCKPIN SCKn input pin is used as Serial Clock n source 1 SLOTSIZE Slot Size 0 2 SLOTSIZESelect 8 8-bit Slot for Clock Unit n 0 16 16-bit Slot for Clock Unit n 1 24 24-bit Slot for Clock Unit n 2 32 32-bit Slot for Clock Unit n 3 CTRLA Control A 0x0 8 read-write n 0x0 0x0 CKEN0 Clock Unit 0 Enable 2 1 CKEN1 Clock Unit 1 Enable 3 1 ENABLE Enable 1 1 RXEN Rx Serializer Enable 5 1 SWRST Software Reset 0 1 TXEN Tx Serializer Enable 4 1 INTENCLR Interrupt Enable Clear 0xC 16 read-write n 0x0 0x0 RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTENSET Interrupt Enable Set 0x10 16 read-write n 0x0 0x0 RXOR0 Receive Overrun 0 Interrupt Enable 4 1 RXOR1 Receive Overrun 1 Interrupt Enable 5 1 RXRDY0 Receive Ready 0 Interrupt Enable 0 1 RXRDY1 Receive Ready 1 Interrupt Enable 1 1 TXRDY0 Transmit Ready 0 Interrupt Enable 8 1 TXRDY1 Transmit Ready 1 Interrupt Enable 9 1 TXUR0 Transmit Underrun 0 Interrupt Enable 12 1 TXUR1 Transmit Underrun 1 Interrupt Enable 13 1 INTFLAG Interrupt Flag Status and Clear 0x14 16 read-write n 0x0 0x0 RXOR0 Receive Overrun 0 4 1 RXOR1 Receive Overrun 1 5 1 RXRDY0 Receive Ready 0 0 1 RXRDY1 Receive Ready 1 1 1 TXRDY0 Transmit Ready 0 8 1 TXRDY1 Transmit Ready 1 9 1 TXUR0 Transmit Underrun 0 12 1 TXUR1 Transmit Underrun 1 13 1 RXCTRL Rx Serializer Control 0x24 32 read-write n 0x0 0x0 BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0 LSBIT Transfer Data Least Significant Bit (LSB) first 1 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0 CLK1 Use Clock Unit 1 1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0 24 24 bits 1 20 20 bits 2 18 18 bits 3 16 16 bits 4 16C 16 bits compact stereo 5 8 8 bits 6 8C 8 bits compact stereo 7 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0 MULTIPLE One DMA channel per data channel 1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0 ONE Extend with ones 1 MSBIT Extend with Most Significant Bit 2 LSBIT Extend with Least Significant Bit 3 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0 MONO Left channel data is duplicated to right channel 1 RXLOOP Loop-back Test Mode 26 1 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0 PDM2 Receive one PDM data on each serial clock edge 2 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0 LEFT Data is left adjusted in slot 1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0 LEFT Data is left adjusted in word 1 RXDATA Rx Data 0x34 32 read-only n 0x0 0x0 DATA Sample Data 0 32 SYNCBUSY Synchronization Status 0x18 16 read-only n 0x0 0x0 CKEN0 Clock Unit 0 Enable Synchronization Status 2 1 CKEN1 Clock Unit 1 Enable Synchronization Status 3 1 ENABLE Enable Synchronization Status 1 1 RXDATA Rx Data Synchronization Status 9 1 RXEN Rx Serializer Enable Synchronization Status 5 1 SWRST Software Reset Synchronization Status 0 1 TXDATA Tx Data Synchronization Status 8 1 TXEN Tx Serializer Enable Synchronization Status 4 1 TXCTRL Tx Serializer Control 0x20 32 read-write n 0x0 0x0 BITREV Data Formatting Bit Reverse 15 1 BITREVSelect MSBIT Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) 0 LSBIT Transfer Data Least Significant Bit (LSB) first 1 CLKSEL Clock Unit Selection 5 1 CLKSELSelect CLK0 Use Clock Unit 0 0 CLK1 Use Clock Unit 1 1 DATASIZE Data Word Size 8 3 DATASIZESelect 32 32 bits 0 24 24 bits 1 20 20 bits 2 18 18 bits 3 16 16 bits 4 16C 16 bits compact stereo 5 8 8 bits 6 8C 8 bits compact stereo 7 DMA Single or Multiple DMA Channels 25 1 DMASelect SINGLE Single DMA channel 0 MULTIPLE One DMA channel per data channel 1 EXTEND Data Formatting Bit Extension 13 2 EXTENDSelect ZERO Extend with zeroes 0 ONE Extend with ones 1 MSBIT Extend with Most Significant Bit 2 LSBIT Extend with Least Significant Bit 3 MONO Mono Mode 24 1 MONOSelect STEREO Normal mode 0 MONO Left channel data is duplicated to right channel 1 SERMODE Serializer Mode 0 2 SERMODESelect RX Receive 0 TX Transmit 1 PDM2 Receive one PDM data on each serial clock edge 2 SLOTADJ Data Slot Formatting Adjust 7 1 SLOTADJSelect RIGHT Data is right adjusted in slot 0 LEFT Data is left adjusted in slot 1 SLOTDIS0 Slot 0 Disabled for this Serializer 16 1 SLOTDIS1 Slot 1 Disabled for this Serializer 17 1 SLOTDIS2 Slot 2 Disabled for this Serializer 18 1 SLOTDIS3 Slot 3 Disabled for this Serializer 19 1 SLOTDIS4 Slot 4 Disabled for this Serializer 20 1 SLOTDIS5 Slot 5 Disabled for this Serializer 21 1 SLOTDIS6 Slot 6 Disabled for this Serializer 22 1 SLOTDIS7 Slot 7 Disabled for this Serializer 23 1 TXDEFAULT Line Default Line when Slot Disabled 2 2 TXDEFAULTSelect ZERO Output Default Value is 0 0 ONE Output Default Value is 1 1 HIZ Output Default Value is high impedance 3 TXSAME Transmit Data when Underrun 4 1 TXSAMESelect ZERO Zero data transmitted in case of underrun 0 SAME Last data transmitted in case of underrun 1 WORDADJ Data Word Formatting Adjust 12 1 WORDADJSelect RIGHT Data is right adjusted in word 0 LEFT Data is left adjusted in word 1 TXDATA Tx Data 0x30 32 write-only n 0x0 0x0 DATA Sample Data 0 32 ICM Integrity Check Monitor ICM 0x0 0x0 0x58 registers n ICM 132 CFG Configuration 0x0 32 read-write n 0x0 0x0 ASCD Automatic Switch To Compare Digest 8 1 BBC Bus Burden Control 4 4 DAPROT Region Descriptor Area Protection 24 6 DUALBUFF Dual Input Buffer 9 1 EOMDIS End of Monitoring Disable 1 1 HAPROT Region Hash Area Protection 16 6 SLBDIS Secondary List Branching Disable 2 1 UALGO User SHA Algorithm 13 3 UALGOSelect SHA1 SHA1 Algorithm 0 SHA256 SHA256 Algorithm 1 SHA224 SHA224 Algorithm 4 UIHASH User Initial Hash Value 12 1 WBDIS Write Back Disable 0 1 CTRL Control 0x4 32 write-only n 0x0 0x0 DISABLE ICM Disable Register 1 1 ENABLE ICM Enable 0 1 REHASH Recompute Internal Hash 4 4 RMDIS Region Monitoring Disable 8 4 RMEN Region Monitoring Enable 12 4 SWRST Software Reset 2 1 DSCR Region Descriptor Area Start Address 0x30 32 read-write n 0x0 0x0 DASA Descriptor Area Start Address 6 26 HASH Region Hash Area Start Address 0x34 32 read-write n 0x0 0x0 HASA Hash Area Start Address 7 25 IDR Interrupt Disable 0x14 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Disable 8 4 RDM Region Digest Mismatch Interrupt Disable 4 4 REC Region End bit Condition detected Interrupt Disable 16 4 RHC Region Hash Completed Interrupt Disable 0 4 RSU Region Status Updated Interrupt Disable 20 4 RWC Region Wrap Condition Detected Interrupt Disable 12 4 URAD Undefined Register Access Detection Interrupt Disable 24 1 IER Interrupt Enable 0x10 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Enable 8 4 RDM Region Digest Mismatch Interrupt Enable 4 4 REC Region End bit Condition Detected Interrupt Enable 16 4 RHC Region Hash Completed Interrupt Enable 0 4 RSU Region Status Updated Interrupt Disable 20 4 RWC Region Wrap Condition detected Interrupt Enable 12 4 URAD Undefined Register Access Detection Interrupt Enable 24 1 IMR Interrupt Mask 0x18 32 read-only n 0x0 0x0 RBE Region Bus Error Interrupt Mask 8 4 RDM Region Digest Mismatch Interrupt Mask 4 4 REC Region End bit Condition Detected Interrupt Mask 16 4 RHC Region Hash Completed Interrupt Mask 0 4 RSU Region Status Updated Interrupt Mask 20 4 RWC Region Wrap Condition Detected Interrupt Mask 12 4 URAD Undefined Register Access Detection Interrupt Mask 24 1 ISR Interrupt Status 0x1C 32 read-only n 0x0 0x0 RBE Region Bus Error 8 4 RDM Region Digest Mismatch 4 4 REC Region End bit Condition Detected 16 4 RHC Region Hash Completed 0 4 RSU Region Status Updated Detected 20 4 RWC Region Wrap Condition Detected 12 4 URAD Undefined Register Access Detection Status 24 1 SR Status 0x8 32 read-only n 0x0 0x0 ENABLE ICM Controller Enable Register 0 1 RAWRMDIS RAW Region Monitoring Disabled Status 8 4 RMDIS Region Monitoring Disabled Status 12 4 UASR Undefined Access Status 0x20 32 read-only n 0x0 0x0 URAT Undefined Register Access Trace 0 3 URATSelect UNSPEC_STRUCT_MEMBER Unspecified structure member set to one detected when the descriptor is loaded 0 CFG_MODIFIED CFG modified during active monitoring 1 DSCR_MODIFIED DSCR modified during active monitoring 2 HASH_MODIFIED HASH modified during active monitoring 3 READ_ACCESS Write-only register read access 4 UIHVAL0 User Initial Hash Value n 0x38 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL1 User Initial Hash Value n 0x3C 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL2 User Initial Hash Value n 0x40 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL3 User Initial Hash Value n 0x44 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL4 User Initial Hash Value n 0x48 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL5 User Initial Hash Value n 0x4C 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL6 User Initial Hash Value n 0x50 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL7 User Initial Hash Value n 0x54 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[0] User Initial Hash Value n 0x70 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[1] User Initial Hash Value n 0xAC 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[2] User Initial Hash Value n 0xEC 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[3] User Initial Hash Value n 0x130 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[4] User Initial Hash Value n 0x178 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[5] User Initial Hash Value n 0x1C4 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[6] User Initial Hash Value n 0x214 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[7] User Initial Hash Value n 0x268 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 ITM Instrumentation Trace Macrocell ITM 0x0 0x0 0x1000 registers n CID0 ITM Component Identification Register #0 0xFF0 32 read-only n 0x0 0x0 CID1 ITM Component Identification Register #1 0xFF4 32 read-only n 0x0 0x0 CID2 ITM Component Identification Register #2 0xFF8 32 read-only n 0x0 0x0 CID3 ITM Component Identification Register #3 0xFFC 32 read-only n 0x0 0x0 IRR ITM Integration Read Register 0xEFC 32 read-only n 0x0 0x0 ATREADYM 0 1 IWR ITM Integration Write Register 0xEF8 32 write-only n 0x0 0x0 ATVALIDM 0 1 PID0 ITM Peripheral Identification Register #0 0xFE0 32 read-only n 0x0 0x0 PID1 ITM Peripheral Identification Register #1 0xFE4 32 read-only n 0x0 0x0 PID2 ITM Peripheral Identification Register #2 0xFE8 32 read-only n 0x0 0x0 PID3 ITM Peripheral Identification Register #3 0xFEC 32 read-only n 0x0 0x0 PID4 ITM Peripheral Identification Register #4 0xFD0 32 read-only n 0x0 0x0 PID5 ITM Peripheral Identification Register #5 0xFD4 32 read-only n 0x0 0x0 PID6 ITM Peripheral Identification Register #6 0xFD8 32 read-only n 0x0 0x0 PID7 ITM Peripheral Identification Register #7 0xFDC 32 read-only n 0x0 0x0 PORT_BYTE_MODE0 ITM Stimulus Port Registers 0x0 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE1 ITM Stimulus Port Registers 0x4 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE10 ITM Stimulus Port Registers 0x28 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE11 ITM Stimulus Port Registers 0x2C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE12 ITM Stimulus Port Registers 0x30 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE13 ITM Stimulus Port Registers 0x34 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE14 ITM Stimulus Port Registers 0x38 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE15 ITM Stimulus Port Registers 0x3C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE16 ITM Stimulus Port Registers 0x40 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE17 ITM Stimulus Port Registers 0x44 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE18 ITM Stimulus Port Registers 0x48 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE19 ITM Stimulus Port Registers 0x4C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE2 ITM Stimulus Port Registers 0x8 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE20 ITM Stimulus Port Registers 0x50 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE21 ITM Stimulus Port Registers 0x54 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE22 ITM Stimulus Port Registers 0x58 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE23 ITM Stimulus Port Registers 0x5C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE24 ITM Stimulus Port Registers 0x60 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE25 ITM Stimulus Port Registers 0x64 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE26 ITM Stimulus Port Registers 0x68 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE27 ITM Stimulus Port Registers 0x6C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE28 ITM Stimulus Port Registers 0x70 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE29 ITM Stimulus Port Registers 0x74 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE3 ITM Stimulus Port Registers 0xC 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE30 ITM Stimulus Port Registers 0x78 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE31 ITM Stimulus Port Registers 0x7C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE4 ITM Stimulus Port Registers 0x10 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE5 ITM Stimulus Port Registers 0x14 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE6 ITM Stimulus Port Registers 0x18 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE7 ITM Stimulus Port Registers 0x1C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE8 ITM Stimulus Port Registers 0x20 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE9 ITM Stimulus Port Registers 0x24 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[0] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x0 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[10] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0xDC 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[11] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x108 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[12] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x138 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[13] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x16C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[14] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x1A4 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[15] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x1E0 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[16] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x220 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[17] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x264 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[18] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x2AC 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[19] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x2F8 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[1] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x4 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[20] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x348 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[21] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x39C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[22] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x3F4 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[23] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x450 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[24] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x4B0 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[25] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x514 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[26] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x57C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[27] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x5E8 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[28] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x658 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[29] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x6CC 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[2] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0xC 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[30] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x744 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[31] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x7C0 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[3] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x18 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[4] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x28 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[5] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x3C 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[6] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x54 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[7] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x70 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[8] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x90 32 write-only n 0x0 0x0 PORT 0 8 PORT_BYTE_MODE[9] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0xB4 32 write-only n 0x0 0x0 PORT 0 8 PORT_HWORD_MODE0 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x0 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE1 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x4 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE10 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x28 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE11 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x2C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE12 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x30 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE13 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x34 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE14 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x38 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE15 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x3C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE16 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x40 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE17 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x44 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE18 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x48 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE19 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x4C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE2 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x8 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE20 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x50 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE21 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x54 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE22 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x58 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE23 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x5C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE24 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x60 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE25 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x64 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE26 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x68 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE27 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x6C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE28 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x70 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE29 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x74 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE3 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0xC 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE30 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x78 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE31 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x7C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE4 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x10 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE5 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x14 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE6 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x18 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE7 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x1C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE8 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x20 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE9 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x24 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[0] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x0 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[10] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0xDC 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[11] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x108 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[12] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x138 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[13] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x16C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[14] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x1A4 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[15] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x1E0 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[16] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x220 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[17] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x264 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[18] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x2AC 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[19] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x2F8 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[1] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x4 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[20] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x348 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[21] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x39C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[22] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x3F4 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[23] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x450 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[24] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x4B0 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[25] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x514 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[26] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x57C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[27] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x5E8 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[28] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x658 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[29] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x6CC 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[2] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0xC 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[30] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x744 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[31] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x7C0 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[3] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x18 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[4] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x28 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[5] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x3C 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[6] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x54 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[7] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x70 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[8] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0x90 32 write-only n 0x0 0x0 PORT 0 16 PORT_HWORD_MODE[9] ITM Stimulus Port Registers PORT_WORD_MODE[%s] 0xB4 32 write-only n 0x0 0x0 PORT 0 16 PORT_WORD_MODE0 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x0 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE1 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x4 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE10 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x28 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE11 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x2C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE12 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x30 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE13 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x34 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE14 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x38 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE15 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x3C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE16 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x40 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE17 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x44 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE18 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x48 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE19 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x4C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE2 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x8 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE20 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x50 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE21 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x54 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE22 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x58 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE23 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x5C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE24 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x60 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE25 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x64 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE26 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x68 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE27 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x6C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE28 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x70 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE29 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x74 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE3 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0xC 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE30 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x78 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE31 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x7C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE4 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x10 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE5 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x14 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE6 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x18 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE7 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x1C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE8 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x20 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE9 ITM Stimulus Port Registers PORT_BYTE_MODE[%s] 0x24 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[0] ITM Stimulus Port Registers 0x0 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[10] ITM Stimulus Port Registers 0xDC 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[11] ITM Stimulus Port Registers 0x108 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[12] ITM Stimulus Port Registers 0x138 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[13] ITM Stimulus Port Registers 0x16C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[14] ITM Stimulus Port Registers 0x1A4 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[15] ITM Stimulus Port Registers 0x1E0 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[16] ITM Stimulus Port Registers 0x220 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[17] ITM Stimulus Port Registers 0x264 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[18] ITM Stimulus Port Registers 0x2AC 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[19] ITM Stimulus Port Registers 0x2F8 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[1] ITM Stimulus Port Registers 0x4 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[20] ITM Stimulus Port Registers 0x348 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[21] ITM Stimulus Port Registers 0x39C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[22] ITM Stimulus Port Registers 0x3F4 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[23] ITM Stimulus Port Registers 0x450 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[24] ITM Stimulus Port Registers 0x4B0 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[25] ITM Stimulus Port Registers 0x514 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[26] ITM Stimulus Port Registers 0x57C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[27] ITM Stimulus Port Registers 0x5E8 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[28] ITM Stimulus Port Registers 0x658 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[29] ITM Stimulus Port Registers 0x6CC 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[2] ITM Stimulus Port Registers 0xC 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[30] ITM Stimulus Port Registers 0x744 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[31] ITM Stimulus Port Registers 0x7C0 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[3] ITM Stimulus Port Registers 0x18 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[4] ITM Stimulus Port Registers 0x28 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[5] ITM Stimulus Port Registers 0x3C 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[6] ITM Stimulus Port Registers 0x54 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[7] ITM Stimulus Port Registers 0x70 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[8] ITM Stimulus Port Registers 0x90 32 write-only n 0x0 0x0 PORT 0 32 PORT_WORD_MODE[9] ITM Stimulus Port Registers 0xB4 32 write-only n 0x0 0x0 PORT 0 32 TCR ITM Trace Control Register 0xE80 32 read-write n 0x0 0x0 BUSY 23 1 DWTENA 3 1 GTSFREQ 10 2 ITMENA 0 1 STALLENA 5 1 SWOENA 4 1 SYNCENA 2 1 TraceBusID 16 7 TSENA 1 1 TSPrescale 8 2 TER ITM Trace Enable Register 0xE00 32 read-write n 0x0 0x0 TPR ITM Trace Privilege Register 0xE40 32 read-write n 0x0 0x0 PRIVMASK 0 4 MCLK Main Clock MCLK 0x0 0x0 0x24 registers n MCLK 1 AHBMASK AHB Mask 0x10 32 read-write n 0x0 0x0 BKUPRAM_ BKUPRAM AHB Clock Mask 11 1 CMCC_ CMCC AHB Clock Mask 8 1 DMAC_ DMAC AHB Clock Mask 9 1 DSU_ DSU AHB Clock Mask 4 1 GMAC_ GMAC AHB Clock Mask 14 1 HMATRIX_ HMATRIX AHB Clock Mask 5 1 HPB0_ HPB0 AHB Clock Mask 0 1 HPB1_ HPB1 AHB Clock Mask 1 1 HPB2_ HPB2 AHB Clock Mask 2 1 HPB3_ HPB3 AHB Clock Mask 3 1 HSRAM_ HSRAM AHB Clock Mask 7 1 ICM_ ICM AHB Clock Mask 19 1 NVMCTRL_ NVMCTRL AHB Clock Mask 6 1 NVMCTRL_CACHE_ NVMCTRL_CACHE AHB Clock Mask 23 1 NVMCTRL_SMEEPROM_ NVMCTRL_SMEEPROM AHB Clock Mask 22 1 PAC_ PAC AHB Clock Mask 12 1 PUKCC_ PUKCC AHB Clock Mask 20 1 QSPI_ QSPI AHB Clock Mask 13 1 QSPI_2X_ QSPI_2X AHB Clock Mask 21 1 SDHC0_ SDHC0 AHB Clock Mask 15 1 USB_ USB AHB Clock Mask 10 1 APBAMASK APBA Mask 0x14 32 read-write n 0x0 0x0 EIC_ EIC APB Clock Enable 10 1 FREQM_ FREQM APB Clock Enable 11 1 GCLK_ GCLK APB Clock Enable 7 1 MCLK_ MCLK APB Clock Enable 2 1 OSC32KCTRL_ OSC32KCTRL APB Clock Enable 5 1 OSCCTRL_ OSCCTRL APB Clock Enable 4 1 PAC_ PAC APB Clock Enable 0 1 PM_ PM APB Clock Enable 1 1 RSTC_ RSTC APB Clock Enable 3 1 RTC_ RTC APB Clock Enable 9 1 SERCOM0_ SERCOM0 APB Clock Enable 12 1 SERCOM1_ SERCOM1 APB Clock Enable 13 1 SUPC_ SUPC APB Clock Enable 6 1 TC0_ TC0 APB Clock Enable 14 1 TC1_ TC1 APB Clock Enable 15 1 WDT_ WDT APB Clock Enable 8 1 APBBMASK APBB Mask 0x18 32 read-write n 0x0 0x0 DSU_ DSU APB Clock Enable 1 1 EVSYS_ EVSYS APB Clock Enable 7 1 HMATRIX_ HMATRIX APB Clock Enable 6 1 NVMCTRL_ NVMCTRL APB Clock Enable 2 1 PORT_ PORT APB Clock Enable 4 1 RAMECC_ RAMECC APB Clock Enable 16 1 SERCOM2_ SERCOM2 APB Clock Enable 9 1 SERCOM3_ SERCOM3 APB Clock Enable 10 1 TC2_ TC2 APB Clock Enable 13 1 TC3_ TC3 APB Clock Enable 14 1 TCC0_ TCC0 APB Clock Enable 11 1 TCC1_ TCC1 APB Clock Enable 12 1 USB_ USB APB Clock Enable 0 1 APBCMASK APBC Mask 0x1C 32 read-write n 0x0 0x0 AC_ AC APB Clock Enable 8 1 AES_ AES APB Clock Enable 9 1 CCL_ CCL APB Clock Enable 14 1 GMAC_ GMAC APB Clock Enable 2 1 ICM_ ICM APB Clock Enable 11 1 PDEC_ PDEC APB Clock Enable 7 1 QSPI_ QSPI APB Clock Enable 13 1 TC4_ TC4 APB Clock Enable 5 1 TC5_ TC5 APB Clock Enable 6 1 TCC2_ TCC2 APB Clock Enable 3 1 TCC3_ TCC3 APB Clock Enable 4 1 TRNG_ TRNG APB Clock Enable 10 1 APBDMASK APBD Mask 0x20 32 read-write n 0x0 0x0 ADC0_ ADC0 APB Clock Enable 7 1 ADC1_ ADC1 APB Clock Enable 8 1 DAC_ DAC APB Clock Enable 9 1 I2S_ I2S APB Clock Enable 10 1 PCC_ PCC APB Clock Enable 11 1 SERCOM4_ SERCOM4 APB Clock Enable 0 1 SERCOM5_ SERCOM5 APB Clock Enable 1 1 TCC4_ TCC4 APB Clock Enable 4 1 CPUDIV CPU Clock Division 0x5 8 read-write n 0x0 0x0 DIV Low-Power Clock Division Factor 0 8 DIVSelect DIV1 Divide by 1 1 DIV128 Divide by 128 128 DIV16 Divide by 16 16 DIV2 Divide by 2 2 DIV32 Divide by 32 32 DIV4 Divide by 4 4 DIV64 Divide by 64 64 DIV8 Divide by 8 8 HSDIV HS Clock Division 0x4 8 read-only n 0x0 0x0 DIV CPU Clock Division Factor 0 8 DIVSelect DIV1 Divide by 1 1 INTENCLR Interrupt Enable Clear 0x1 8 read-write n 0x0 0x0 CKRDY Clock Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x2 8 read-write n 0x0 0x0 CKRDY Clock Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x3 8 read-write n 0x0 0x0 CKRDY Clock Ready 0 1 MPU Memory Protection Unit MPU 0x0 0x0 0x2C registers n CTRL MPU Control Register 0x4 32 read-write n 0x0 0x0 ENABLE MPU Enable 0 1 HFNMIENA Enable Hard Fault and NMI handlers 1 1 PRIVDEFENA Enables privileged software access to default memory map 2 1 RASR MPU Region Attribute and Size Register 0x10 32 read-write n 0x0 0x0 AP Access Permission 24 3 B Bufferable bit 16 1 C Cacheable bit 17 1 ENABLE Region Enable 0 1 S Shareable bit 18 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 TEX TEX bit 19 3 XN Execute Never Attribute 28 1 RASR_A1 MPU Alias 1 Region Attribute and Size Register 0x18 32 read-write n 0x0 0x0 AP Access Permission 24 3 B Bufferable bit 16 1 C Cacheable bit 17 1 ENABLE Region Enable 0 1 S Shareable bit 18 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 TEX TEX bit 19 3 XN Execute Never Attribute 28 1 RASR_A2 MPU Alias 2 Region Attribute and Size Register 0x20 32 read-write n 0x0 0x0 AP Access Permission 24 3 B Bufferable bit 16 1 C Cacheable bit 17 1 ENABLE Region Enable 0 1 S Shareable bit 18 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 TEX TEX bit 19 3 XN Execute Never Attribute 28 1 RASR_A3 MPU Alias 3 Region Attribute and Size Register 0x28 32 read-write n 0x0 0x0 AP Access Permission 24 3 B Bufferable bit 16 1 C Cacheable bit 17 1 ENABLE Region Enable 0 1 S Shareable bit 18 1 SIZE Region Size 1 1 SRD Sub-region disable 8 8 TEX TEX bit 19 3 XN Execute Never Attribute 28 1 RBAR MPU Region Base Address Register 0xC 32 read-write n 0x0 0x0 ADDR Region base address 5 27 REGION Region number 0 4 VALID Region number valid 4 1 RBAR_A1 MPU Alias 1 Region Base Address Register 0x14 32 read-write n 0x0 0x0 ADDR Region base address 5 27 REGION Region number 0 4 VALID Region number valid 4 1 RBAR_A2 MPU Alias 2 Region Base Address Register 0x1C 32 read-write n 0x0 0x0 ADDR Region base address 5 27 REGION Region number 0 4 VALID Region number valid 4 1 RBAR_A3 MPU Alias 3 Region Base Address Register 0x24 32 read-write n 0x0 0x0 ADDR Region base address 5 27 REGION Region number 0 4 VALID Region number valid 4 1 RNR MPU Region Number Register 0x8 32 read-write n 0x0 0x0 REGION Region referenced by RBAR and RASR 0 8 TYPE MPU Type Register 0x0 32 read-only n 0x0 0x0 DREGION Number of Data Regions 8 8 IREGION Number of Instruction Regions 16 8 SEPARATE Separate instruction and Data Memory MapsRegions 0 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0xE04 registers n IABR0 Interrupt Active Bit Register 0x200 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR1 Interrupt Active Bit Register 0x204 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR2 Interrupt Active Bit Register 0x208 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR3 Interrupt Active Bit Register 0x20C 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR4 Interrupt Active Bit Register 0x210 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR[0] Interrupt Active Bit Register 0x400 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR[1] Interrupt Active Bit Register 0x604 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR[2] Interrupt Active Bit Register 0x80C 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR[3] Interrupt Active Bit Register 0xA18 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 IABR[4] Interrupt Active Bit Register 0xC28 32 read-write n 0x0 0x0 ACTIVE Interrupt active bits 0 32 ICER0 Interrupt Clear Enable Register 0x80 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER1 Interrupt Clear Enable Register 0x84 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER2 Interrupt Clear Enable Register 0x88 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER3 Interrupt Clear Enable Register 0x8C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER4 Interrupt Clear Enable Register 0x90 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[0] Interrupt Clear Enable Register 0x100 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[1] Interrupt Clear Enable Register 0x184 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[2] Interrupt Clear Enable Register 0x20C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[3] Interrupt Clear Enable Register 0x298 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[4] Interrupt Clear Enable Register 0x328 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICPR0 Interrupt Clear Pending Register 0x180 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR1 Interrupt Clear Pending Register 0x184 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR2 Interrupt Clear Pending Register 0x188 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR3 Interrupt Clear Pending Register 0x18C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR4 Interrupt Clear Pending Register 0x190 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[0] Interrupt Clear Pending Register 0x300 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[1] Interrupt Clear Pending Register 0x484 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[2] Interrupt Clear Pending Register 0x60C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[3] Interrupt Clear Pending Register 0x798 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[4] Interrupt Clear Pending Register 0x928 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 IP0 Interrupt Priority Register n 0x300 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP1 Interrupt Priority Register n 0x301 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP10 Interrupt Priority Register n 0x30A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP11 Interrupt Priority Register n 0x30B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP12 Interrupt Priority Register n 0x30C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP13 Interrupt Priority Register n 0x30D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP14 Interrupt Priority Register n 0x30E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP15 Interrupt Priority Register n 0x30F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP16 Interrupt Priority Register n 0x310 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP17 Interrupt Priority Register n 0x311 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP18 Interrupt Priority Register n 0x312 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP19 Interrupt Priority Register n 0x313 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP2 Interrupt Priority Register n 0x302 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP20 Interrupt Priority Register n 0x314 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP21 Interrupt Priority Register n 0x315 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP22 Interrupt Priority Register n 0x316 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP23 Interrupt Priority Register n 0x317 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP24 Interrupt Priority Register n 0x318 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP25 Interrupt Priority Register n 0x319 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP26 Interrupt Priority Register n 0x31A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP27 Interrupt Priority Register n 0x31B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP28 Interrupt Priority Register n 0x31C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP29 Interrupt Priority Register n 0x31D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP3 Interrupt Priority Register n 0x303 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP30 Interrupt Priority Register n 0x31E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP31 Interrupt Priority Register n 0x31F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP32 Interrupt Priority Register n 0x320 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP33 Interrupt Priority Register n 0x321 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP34 Interrupt Priority Register n 0x322 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP4 Interrupt Priority Register n 0x304 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP5 Interrupt Priority Register n 0x305 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP6 Interrupt Priority Register n 0x306 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP7 Interrupt Priority Register n 0x307 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP8 Interrupt Priority Register n 0x308 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP9 Interrupt Priority Register n 0x309 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[0] Interrupt Priority Register n 0x600 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[10] Interrupt Priority Register n 0x2437 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[11] Interrupt Priority Register n 0x2742 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[12] Interrupt Priority Register n 0x2A4E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[13] Interrupt Priority Register n 0x2D5B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[14] Interrupt Priority Register n 0x3069 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[15] Interrupt Priority Register n 0x3378 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[16] Interrupt Priority Register n 0x3688 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[17] Interrupt Priority Register n 0x3999 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[18] Interrupt Priority Register n 0x3CAB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[19] Interrupt Priority Register n 0x3FBE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[1] Interrupt Priority Register n 0x901 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[20] Interrupt Priority Register n 0x42D2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[21] Interrupt Priority Register n 0x45E7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[22] Interrupt Priority Register n 0x48FD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[23] Interrupt Priority Register n 0x4C14 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[24] Interrupt Priority Register n 0x4F2C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[25] Interrupt Priority Register n 0x5245 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[26] Interrupt Priority Register n 0x555F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[27] Interrupt Priority Register n 0x587A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[28] Interrupt Priority Register n 0x5B96 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[29] Interrupt Priority Register n 0x5EB3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[2] Interrupt Priority Register n 0xC03 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[30] Interrupt Priority Register n 0x61D1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[31] Interrupt Priority Register n 0x64F0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[32] Interrupt Priority Register n 0x6810 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[33] Interrupt Priority Register n 0x6B31 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[34] Interrupt Priority Register n 0x6E53 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[3] Interrupt Priority Register n 0xF06 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[4] Interrupt Priority Register n 0x120A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[5] Interrupt Priority Register n 0x150F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[6] Interrupt Priority Register n 0x1815 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[7] Interrupt Priority Register n 0x1B1C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[8] Interrupt Priority Register n 0x1E24 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 IP[9] Interrupt Priority Register n 0x212D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt n 0 3 ISER0 Interrupt Set Enable Register 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER1 Interrupt Set Enable Register 0x4 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER2 Interrupt Set Enable Register 0x8 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER3 Interrupt Set Enable Register 0xC 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER4 Interrupt Set Enable Register 0x10 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[0] Interrupt Set Enable Register 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[1] Interrupt Set Enable Register 0x4 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[2] Interrupt Set Enable Register 0xC 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[3] Interrupt Set Enable Register 0x18 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[4] Interrupt Set Enable Register 0x28 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISPR0 Interrupt Set Pending Register 0x100 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR1 Interrupt Set Pending Register 0x104 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR2 Interrupt Set Pending Register 0x108 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR3 Interrupt Set Pending Register 0x10C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR4 Interrupt Set Pending Register 0x110 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[0] Interrupt Set Pending Register 0x200 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[1] Interrupt Set Pending Register 0x304 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[2] Interrupt Set Pending Register 0x40C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[3] Interrupt Set Pending Register 0x518 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[4] Interrupt Set Pending Register 0x628 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 STIR Software Trigger Interrupt Register 0xE00 32 write-only n 0x0 0x0 INTID Interrupt ID to trigger 0 9 NVMCTRL Non-Volatile Memory Controller NVMCTRL 0x0 0x0 0x30 registers n NVMCTRL_0 29 NVMCTRL_1 30 ADDR Address 0x14 32 read-write n 0x0 0x0 ADDR NVM Address 0 24 CTRLA Control A 0x0 16 read-write n 0x0 0x0 AHBNS0 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated 12 1 AHBNS1 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated 13 1 AUTOWS Auto Wait State Enable 2 1 CACHEDIS0 AHB0 Cache Disable 14 1 CACHEDIS1 AHB1 Cache Disable 15 1 PRM Power Reduction Mode during Sleep 6 2 PRMSelect SEMIAUTO NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. 0 FULLAUTO NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. 1 MANUAL NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. 3 RWS NVM Read Wait States 8 4 SUSPEN Suspend Enable 3 1 WMODE Write Mode 4 2 WMODESelect MAN Manual Write 0 ADW Automatic Double Word Write 1 AQW Automatic Quad Word 2 AP Automatic Page Write 3 CTRLB Control B 0x4 16 write-only n 0x0 0x0 CMD Command 0 7 CMDSelect EP Erase Page - Only supported in the USER and AUX pages. 0 EB Erase Block - Erases the block addressed by the ADDR register, not supported in the user page 1 SWRST Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers 16 LR Lock Region - Locks the region containing the address location in the ADDR register. 17 UR Unlock Region - Unlocks the region containing the address location in the ADDR register. 18 SPRM Sets the power reduction mode. 19 CPRM Clears the power reduction mode. 20 PBC Page Buffer Clear - Clears the page buffer. 21 SSB Set Security Bit 22 BKSWRST Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK 23 CELCK Chip Erase Lock - DSU.CE command is not available 24 CEULCK Chip Erase Unlock - DSU.CE command is available 25 SBPDIS Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence 26 CBPDIS Clears STATUS.BPDIS, Boot loader protection is not discarded 27 WP Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page 3 WQW Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. 4 ASEES0 Activate SmartEEPROM Sector 0, deactivate Sector 1 48 ASEES1 Activate SmartEEPROM Sector 1, deactivate Sector 0 49 SEERALOC Starts SmartEEPROM sector reallocation algorithm 50 SEEFLUSH Flush SMEE data when in buffered mode 51 LSEE Lock access to SmartEEPROM data from any mean 52 USEE Unlock access to SmartEEPROM data 53 LSEER Lock access to the SmartEEPROM Register Address Space (above 64KB) 54 USEER Unlock access to the SmartEEPROM Register Address Space (above 64KB) 55 CMDEX Command Execution 8 8 CMDEXSelect KEY Execution Key 165 DBGCTRL Debug Control 0x28 8 read-write n 0x0 0x0 ECCDIS Debugger ECC Read Disable 0 1 ECCELOG Debugger ECC Error Tracking Mode 1 1 ECCERR ECC Error Status Register 0x24 32 read-only n 0x0 0x0 ADDR Error Address 0 24 TYPEH High Double-Word Error Type 30 2 TYPEHSelect None No Error Detected Since Last Read 0 Single At Least One Single Error Detected Since last Read 1 Dual At Least One Dual Error Detected Since Last Read 2 TYPEL Low Double-Word Error Type 28 2 TYPELSelect None No Error Detected Since Last Read 0 Single At Least One Single Error Detected Since last Read 1 Dual At Least One Dual Error Detected Since Last Read 2 INTENCLR Interrupt Enable Clear 0xC 16 read-write n 0x0 0x0 ADDRE Address Error 1 1 DONE Command Done Interrupt Clear 0 1 ECCDE ECC Dual Error Interrupt Clear 5 1 ECCSE ECC Single Error Interrupt Clear 4 1 LOCKE Lock Error Interrupt Clear 3 1 NVME NVM Error Interrupt Clear 6 1 PROGE Programming Error Interrupt Clear 2 1 SEESFULL Active SEES Full Interrupt Clear 8 1 SEESOVF Active SEES Overflow Interrupt Clear 9 1 SEEWRC SEE Write Completed Interrupt Clear 10 1 SUSP Suspended Write Or Erase Interrupt Clear 7 1 INTENSET Interrupt Enable Set 0xE 16 read-write n 0x0 0x0 ADDRE Address Error Interrupt Enable 1 1 DONE Command Done Interrupt Enable 0 1 ECCDE ECC Dual Error Interrupt Enable 5 1 ECCSE ECC Single Error Interrupt Enable 4 1 LOCKE Lock Error Interrupt Enable 3 1 NVME NVM Error Interrupt Enable 6 1 PROGE Programming Error Interrupt Enable 2 1 SEESFULL Active SEES Full Interrupt Enable 8 1 SEESOVF Active SEES Overflow Interrupt Enable 9 1 SEEWRC SEE Write Completed Interrupt Enable 10 1 SUSP Suspended Write Or Erase Interrupt Enable 7 1 INTFLAG Interrupt Flag Status and Clear 0x10 16 read-write n 0x0 0x0 ADDRE Address Error 1 1 DONE Command Done 0 1 ECCDE ECC Dual Error 5 1 ECCSE ECC Single Error 4 1 LOCKE Lock Error 3 1 NVME NVM Error 6 1 PROGE Programming Error 2 1 SEESFULL Active SEES Full 8 1 SEESOVF Active SEES Overflow 9 1 SEEWRC SEE Write Completed 10 1 SUSP Suspended Write Or Erase Operation 7 1 PARAM NVM Parameter 0x8 32 read-only n 0x0 0x0 NVMP NVM Pages 0 16 PSZ Page Size 16 3 PSZSelect 8 8 bytes 0 16 16 bytes 1 32 32 bytes 2 64 64 bytes 3 128 128 bytes 4 256 256 bytes 5 512 512 bytes 6 1024 1024 bytes 7 SEE SmartEEPROM Supported 31 1 SEESelect 0 0 bytes 0 1 16384 bytes 1 A 163840 bytes 10 2 32768 bytes 2 3 49152 bytes 3 4 65536 bytes 4 5 81920 bytes 5 6 98304 bytes 6 7 114688 bytes 7 8 131072 bytes 8 9 147456 bytes 9 PBLDATA0 Page Buffer Load Data x 0x1C 32 read-only n 0x0 0x0 DATA Page Buffer Data 0 32 PBLDATA1 Page Buffer Load Data x 0x20 32 read-only n 0x0 0x0 DATA Page Buffer Data 0 32 PBLDATA[0] Page Buffer Load Data x 0x38 32 read-only n 0x0 0x0 DATA Page Buffer Data 0 32 PBLDATA[1] Page Buffer Load Data x 0x58 32 read-only n 0x0 0x0 DATA Page Buffer Data 0 32 RUNLOCK Lock Section 0x18 32 read-only n 0x0 0x0 RUNLOCK Region Un-Lock Bits 0 32 SEECFG SmartEEPROM Configuration Register 0x2A 8 read-write n 0x0 0x0 APRDIS Automatic Page Reallocation Disable 1 1 WMODE Write Mode 0 1 WMODESelect UNBUFFERED A NVM write command is issued after each write in the pagebuffer 0 BUFFERED A NVM write command is issued when a write to a new page is requested 1 SEESTAT SmartEEPROM Status Register 0x2C 32 read-only n 0x0 0x0 ASEES Active SmartEEPROM Sector 0 1 BUSY Busy 2 1 LOAD Page Buffer Loaded 1 1 LOCK SmartEEPROM Write Access Is Locked 3 1 PSZ SmartEEPROM Page Size 16 3 RLOCK SmartEEPROM Write Access To Register Address Space Is Locked 4 1 SBLK Blocks Number In a Sector 8 4 STATUS Status 0x12 16 read-only n 0x0 0x0 AFIRST BANKA First 4 1 BOOTPROT Boot Loader Protection Size 8 4 BOOTPROTSelect 120 120 kbytes 0 112 112 kbytes 1 40 40 kbytes 10 32 32 kbytes 11 24 24 kbytes 12 16 16 kbytes 13 8 8 kbytes 14 0 0 kbytes 15 104 104 kbytes 2 96 96 kbytes 3 88 88 kbytes 4 80 80 kbytes 5 72 72 kbytes 6 64 64 kbytes 7 56 56 kbytes 8 48 48 kbytes 9 BPDIS Boot Loader Protection Disable 5 1 LOAD NVM Page Buffer Active Loading 2 1 PRM Power Reduction Mode 1 1 READY Ready to accept a command 0 1 SUSP NVM Write Or Erase Operation Is Suspended 3 1 OSC32KCTRL 32kHz Oscillators Control OSC32KCTRL 0x0 0x0 0x20 registers n OSC32KCTRL 7 CFDCTRL Clock Failure Detector Control 0x16 8 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 0 1 CFDPRESC Clock Failure Detector Prescaler 2 1 SWBACK Clock Switch Back 1 1 EVCTRL Event Control 0x17 8 read-write n 0x0 0x0 CFDEO Clock Failure Detector Event Output Enable 0 1 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 XOSC32KFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 XOSC32KFAIL XOSC32K Clock Failure Detector Interrupt Enable 2 1 XOSC32KRDY XOSC32K Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 XOSC32KFAIL XOSC32K Clock Failure Detector 2 1 XOSC32KRDY XOSC32K Ready 0 1 OSCULP32K 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control 0x1C 32 read-write n 0x0 0x0 CALIB Oscillator Calibration 8 6 EN1K Enable Out 1k 2 1 EN32K Enable Out 32k 1 1 WRTLOCK Write Lock 15 1 RTCCTRL RTC Clock Selection 0x10 8 read-write n 0x0 0x0 RTCSEL RTC Clock Selection 0 3 RTCSELSelect ULP1K 1.024kHz from 32kHz internal ULP oscillator 0 ULP32K 32.768kHz from 32kHz internal ULP oscillator 1 XOSC1K 1.024kHz from 32.768kHz internal oscillator 4 XOSC32K 32.768kHz from 32.768kHz external crystal oscillator 5 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 XOSC32KFAIL XOSC32K Clock Failure Detector 2 1 XOSC32KRDY XOSC32K Ready 0 1 XOSC32KSW XOSC32K Clock switch 3 1 XOSC32K 32kHz External Crystal Oscillator (XOSC32K) Control 0x14 16 read-write n 0x0 0x0 CGM Control Gain Mode 13 2 CGMSelect XT Standard mode 1 HS High Speed mode 2 EN1K 1kHz Output Enable 4 1 EN32K 32kHz Output Enable 3 1 ENABLE Oscillator Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Oscillator Start-Up Time 8 3 STARTUPSelect CYCLE2048 62.6 ms 0 CYCLE4096 125 ms 1 CYCLE16384 500 ms 2 CYCLE32768 1000 ms 3 CYCLE65536 2000 ms 4 CYCLE131072 4000 ms 5 CYCLE262144 8000 ms 6 WRTLOCK Write Lock 12 1 XTALEN Crystal Oscillator Enable 2 1 OSCCTRL Oscillators Control OSCCTRL 0x0 0x0 0x58 registers n OSCCTRL_XOSC0 2 OSCCTRL_XOSC1 3 OSCCTRL_DFLL 4 OSCCTRL_DPLL0 5 OSCCTRL_DPLL1 6 DFLLCTRLA DFLL48M Control A 0x1C 8 read-write n 0x0 0x0 ENABLE DFLL Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 DFLLCTRLB DFLL48M Control B 0x20 8 read-write n 0x0 0x0 BPLCKC Bypass Coarse Lock 6 1 CCDIS Chill Cycle Disable 4 1 LLAW Lose Lock After Wake 2 1 MODE Operating Mode Selection 0 1 QLDIS Quick Lock Disable 5 1 STABLE Stable DFLL Frequency 1 1 USBCRM USB Clock Recovery Mode 3 1 WAITLOCK Wait Lock 7 1 DFLLMUL DFLL48M Multiplier 0x28 32 read-write n 0x0 0x0 CSTEP Coarse Maximum Step 26 6 FSTEP Fine Maximum Step 16 8 MUL DFLL Multiply Factor 0 16 DFLLSYNC DFLL48M Synchronization 0x2C 8 read-write n 0x0 0x0 DFLLCTRLB DFLLCTRLB Synchronization Busy 2 1 DFLLMUL DFLLMUL Synchronization Busy 4 1 DFLLVAL DFLLVAL Synchronization Busy 3 1 ENABLE ENABLE Synchronization Busy 1 1 DFLLVAL DFLL48M Value 0x24 32 read-write n 0x0 0x0 COARSE Coarse Value 10 6 DIFF Multiplication Ratio Difference 16 16 FINE Fine Value 0 8 DPLLCTRLA DPLL Control A 0x0 8 read-write n 0x0 0x0 ENABLE DPLL Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 DPLLCTRLB DPLL Control B 0x8 32 read-write n 0x0 0x0 DCOEN DCO Filter Enable 15 1 DCOFILTER Sigma-Delta DCO Filter Selection 12 3 DCOFILTERSelect FILTER1 Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 0 FILTER2 Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 1 FILTER3 Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 2 FILTER4 Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 3 FILTER5 Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 4 FILTER6 Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 5 FILTER7 Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 6 FILTER8 Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 7 DIV Clock Divider 16 11 FILTER Proportional Integral Filter Selection 0 4 FILTERSelect FILTER1 Bandwidth = 92.7Khz and Damping Factor = 0.76 0 FILTER2 Bandwidth = 131Khz and Damping Factor = 1.08 1 FILTER11 Bandwidth = 23.2Khz and Damping Factor = 0.75 10 FILTER12 Bandwidth = 32.8Khz and Damping Factor = 1.06 11 FILTER13 Bandwidth = 65.6Khz and Damping Factor = 1.07 12 FILTER14 Bandwidth = 92.7Khz and Damping Factor = 1.51 13 FILTER15 Bandwidth = 32.8Khz and Damping Factor = 0.53 14 FILTER16 Bandwidth = 46.4Khz and Damping Factor = 0.75 15 FILTER3 Bandwidth = 46.4Khz and Damping Factor = 0.38 2 FILTER4 Bandwidth = 65.6Khz and Damping Factor = 0.54 3 FILTER5 Bandwidth = 131Khz and Damping Factor = 0.56 4 FILTER6 Bandwidth = 185Khz and Damping Factor = 0.79 5 FILTER7 Bandwidth = 65.6Khz and Damping Factor = 0.28 6 FILTER8 Bandwidth = 92.7Khz and Damping Factor = 0.39 7 FILTER9 Bandwidth = 46.4Khz and Damping Factor = 1.49 8 FILTER10 Bandwidth = 65.6Khz and Damping Factor = 2.11 9 LBYPASS Lock Bypass 11 1 LTIME Lock Time 8 3 LTIMESelect DEFAULT No time-out. Automatic lock 0x0 800US Time-out if no lock within 800us 0x4 900US Time-out if no lock within 900us 0x5 1MS Time-out if no lock within 1ms 0x6 1P1MS Time-out if no lock within 1.1ms 0x7 REFCLK Reference Clock Selection 5 3 REFCLKSelect GCLK Dedicated GCLK clock reference 0x0 XOSC32 XOSC32K clock reference 0x1 XOSC0 XOSC0 clock reference 0x2 XOSC1 XOSC1 clock reference 0x3 WUF Wake Up Fast 4 1 DPLLRATIO DPLL Ratio Control 0x4 32 read-write n 0x0 0x0 LDR Loop Divider Ratio 0 13 LDRFRAC Loop Divider Ratio Fractional Part 16 5 DPLLSTATUS DPLL Status 0x10 32 read-only n 0x0 0x0 CLKRDY DPLL Clock Ready 1 1 LOCK DPLL Lock Status 0 1 DPLLSYNCBUSY DPLL Synchronization Busy 0xC 32 read-only n 0x0 0x0 DPLLRATIO DPLL Loop Divider Ratio Synchronization Status 2 1 ENABLE DPLL Enable Synchronization Status 1 1 DPLL[0]-DPLLCTRLA DPLL Control A 0x30 8 read-write n 0x0 0x0 ENABLE DPLL Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 DPLL[0]-DPLLCTRLB DPLL Control B 0x38 32 read-write n 0x0 0x0 DCOEN DCO Filter Enable 15 1 DCOFILTER Sigma-Delta DCO Filter Selection 12 3 DCOFILTERSelect FILTER1 Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 0 FILTER2 Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 1 FILTER3 Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 2 FILTER4 Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 3 FILTER5 Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 4 FILTER6 Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 5 FILTER7 Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 6 FILTER8 Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 7 DIV Clock Divider 16 11 FILTER Proportional Integral Filter Selection 0 4 FILTERSelect FILTER1 Bandwidth = 92.7Khz and Damping Factor = 0.76 0 FILTER2 Bandwidth = 131Khz and Damping Factor = 1.08 1 FILTER11 Bandwidth = 23.2Khz and Damping Factor = 0.75 10 FILTER12 Bandwidth = 32.8Khz and Damping Factor = 1.06 11 FILTER13 Bandwidth = 65.6Khz and Damping Factor = 1.07 12 FILTER14 Bandwidth = 92.7Khz and Damping Factor = 1.51 13 FILTER15 Bandwidth = 32.8Khz and Damping Factor = 0.53 14 FILTER16 Bandwidth = 46.4Khz and Damping Factor = 0.75 15 FILTER3 Bandwidth = 46.4Khz and Damping Factor = 0.38 2 FILTER4 Bandwidth = 65.6Khz and Damping Factor = 0.54 3 FILTER5 Bandwidth = 131Khz and Damping Factor = 0.56 4 FILTER6 Bandwidth = 185Khz and Damping Factor = 0.79 5 FILTER7 Bandwidth = 65.6Khz and Damping Factor = 0.28 6 FILTER8 Bandwidth = 92.7Khz and Damping Factor = 0.39 7 FILTER9 Bandwidth = 46.4Khz and Damping Factor = 1.49 8 FILTER10 Bandwidth = 65.6Khz and Damping Factor = 2.11 9 LBYPASS Lock Bypass 11 1 LTIME Lock Time 8 3 LTIMESelect DEFAULT No time-out. Automatic lock 0 800US Time-out if no lock within 800us 4 900US Time-out if no lock within 900us 5 1MS Time-out if no lock within 1ms 6 1P1MS Time-out if no lock within 1.1ms 7 REFCLK Reference Clock Selection 5 3 REFCLKSelect GCLK Dedicated GCLK clock reference 0 XOSC32 XOSC32K clock reference 1 XOSC0 XOSC0 clock reference 2 XOSC1 XOSC1 clock reference 3 WUF Wake Up Fast 4 1 DPLL[0]-DPLLRATIO DPLL Ratio Control 0x34 32 read-write n 0x0 0x0 LDR Loop Divider Ratio 0 13 LDRFRAC Loop Divider Ratio Fractional Part 16 5 DPLL[0]-DPLLSTATUS DPLL Status 0x40 32 read-only n 0x0 0x0 CLKRDY DPLL Clock Ready 1 1 LOCK DPLL Lock Status 0 1 DPLL[0]-DPLLSYNCBUSY DPLL Synchronization Busy 0x3C 32 read-only n 0x0 0x0 DPLLRATIO DPLL Loop Divider Ratio Synchronization Status 2 1 ENABLE DPLL Enable Synchronization Status 1 1 DPLL[1]-DPLL[0]-DPLLCTRLA DPLL Control A 0x74 8 read-write n 0x0 0x0 ENABLE DPLL Enable 1 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 DPLL[1]-DPLL[0]-DPLLCTRLB DPLL Control B 0x7C 32 read-write n 0x0 0x0 DCOEN DCO Filter Enable 15 1 DCOFILTER Sigma-Delta DCO Filter Selection 12 3 DCOFILTERSelect FILTER1 Capacitor(pF) = 0.5 and Bandwidth Fn (MHz) = 3.21 0 FILTER2 Capacitor(pF) = 1 and Bandwidth Fn (MHz) = 1.6 1 FILTER3 Capacitor(pF) = 1.5 and Bandwidth Fn (MHz) = 1.1 2 FILTER4 Capacitor(pF) = 2 and Bandwidth Fn (MHz) = 0.8 3 FILTER5 Capacitor(pF) = 2.5 and Bandwidth Fn (MHz) = 0.64 4 FILTER6 Capacitor(pF) = 3 and Bandwidth Fn (MHz) = 0.55 5 FILTER7 Capacitor(pF) = 3.5 and Bandwidth Fn (MHz) = 0.45 6 FILTER8 Capacitor(pF) = 4 and Bandwidth Fn (MHz) = 0.4 7 DIV Clock Divider 16 11 FILTER Proportional Integral Filter Selection 0 4 FILTERSelect FILTER1 Bandwidth = 92.7Khz and Damping Factor = 0.76 0 FILTER2 Bandwidth = 131Khz and Damping Factor = 1.08 1 FILTER11 Bandwidth = 23.2Khz and Damping Factor = 0.75 10 FILTER12 Bandwidth = 32.8Khz and Damping Factor = 1.06 11 FILTER13 Bandwidth = 65.6Khz and Damping Factor = 1.07 12 FILTER14 Bandwidth = 92.7Khz and Damping Factor = 1.51 13 FILTER15 Bandwidth = 32.8Khz and Damping Factor = 0.53 14 FILTER16 Bandwidth = 46.4Khz and Damping Factor = 0.75 15 FILTER3 Bandwidth = 46.4Khz and Damping Factor = 0.38 2 FILTER4 Bandwidth = 65.6Khz and Damping Factor = 0.54 3 FILTER5 Bandwidth = 131Khz and Damping Factor = 0.56 4 FILTER6 Bandwidth = 185Khz and Damping Factor = 0.79 5 FILTER7 Bandwidth = 65.6Khz and Damping Factor = 0.28 6 FILTER8 Bandwidth = 92.7Khz and Damping Factor = 0.39 7 FILTER9 Bandwidth = 46.4Khz and Damping Factor = 1.49 8 FILTER10 Bandwidth = 65.6Khz and Damping Factor = 2.11 9 LBYPASS Lock Bypass 11 1 LTIME Lock Time 8 3 LTIMESelect DEFAULT No time-out. Automatic lock 0 800US Time-out if no lock within 800us 4 900US Time-out if no lock within 900us 5 1MS Time-out if no lock within 1ms 6 1P1MS Time-out if no lock within 1.1ms 7 REFCLK Reference Clock Selection 5 3 REFCLKSelect GCLK Dedicated GCLK clock reference 0 XOSC32 XOSC32K clock reference 1 XOSC0 XOSC0 clock reference 2 XOSC1 XOSC1 clock reference 3 WUF Wake Up Fast 4 1 DPLL[1]-DPLL[0]-DPLLRATIO DPLL Ratio Control 0x78 32 read-write n 0x0 0x0 LDR Loop Divider Ratio 0 13 LDRFRAC Loop Divider Ratio Fractional Part 16 5 DPLL[1]-DPLL[0]-DPLLSTATUS DPLL Status 0x84 32 read-only n 0x0 0x0 CLKRDY DPLL Clock Ready 1 1 LOCK DPLL Lock Status 0 1 DPLL[1]-DPLL[0]-DPLLSYNCBUSY DPLL Synchronization Busy 0x80 32 read-only n 0x0 0x0 DPLLRATIO DPLL Loop Divider Ratio Synchronization Status 2 1 ENABLE DPLL Enable Synchronization Status 1 1 EVCTRL Event Control 0x0 8 read-write n 0x0 0x0 CFDEO0 Clock 0 Failure Detector Event Output Enable 0 1 CFDEO1 Clock 1 Failure Detector Event Output Enable 1 1 INTENCLR Interrupt Enable Clear 0x4 32 read-write n 0x0 0x0 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DPLL0LCKF DPLL0 Lock Fall Interrupt Enable 17 1 DPLL0LCKR DPLL0 Lock Rise Interrupt Enable 16 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete Interrupt Enable 19 1 DPLL0LTO DPLL0 Lock Timeout Interrupt Enable 18 1 DPLL1LCKF DPLL1 Lock Fall Interrupt Enable 25 1 DPLL1LCKR DPLL1 Lock Rise Interrupt Enable 24 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete Interrupt Enable 27 1 DPLL1LTO DPLL1 Lock Timeout Interrupt Enable 26 1 XOSCFAIL0 XOSC 0 Clock Failure Detector Interrupt Enable 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector Interrupt Enable 3 1 XOSCRDY0 XOSC 0 Ready Interrupt Enable 0 1 XOSCRDY1 XOSC 1 Ready Interrupt Enable 1 1 INTENSET Interrupt Enable Set 0x8 32 read-write n 0x0 0x0 DFLLLCKC DFLL Lock Coarse Interrupt Enable 11 1 DFLLLCKF DFLL Lock Fine Interrupt Enable 10 1 DFLLOOB DFLL Out Of Bounds Interrupt Enable 9 1 DFLLRCS DFLL Reference Clock Stopped Interrupt Enable 12 1 DFLLRDY DFLL Ready Interrupt Enable 8 1 DPLL0LCKF DPLL0 Lock Fall Interrupt Enable 17 1 DPLL0LCKR DPLL0 Lock Rise Interrupt Enable 16 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete Interrupt Enable 19 1 DPLL0LTO DPLL0 Lock Timeout Interrupt Enable 18 1 DPLL1LCKF DPLL1 Lock Fall Interrupt Enable 25 1 DPLL1LCKR DPLL1 Lock Rise Interrupt Enable 24 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete Interrupt Enable 27 1 DPLL1LTO DPLL1 Lock Timeout Interrupt Enable 26 1 XOSCFAIL0 XOSC 0 Clock Failure Detector Interrupt Enable 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector Interrupt Enable 3 1 XOSCRDY0 XOSC 0 Ready Interrupt Enable 0 1 XOSCRDY1 XOSC 1 Ready Interrupt Enable 1 1 INTFLAG Interrupt Flag Status and Clear 0xC 32 read-write n 0x0 0x0 DFLLLCKC DFLL Lock Coarse 11 1 DFLLLCKF DFLL Lock Fine 10 1 DFLLOOB DFLL Out Of Bounds 9 1 DFLLRCS DFLL Reference Clock Stopped 12 1 DFLLRDY DFLL Ready 8 1 DPLL0LCKF DPLL0 Lock Fall 17 1 DPLL0LCKR DPLL0 Lock Rise 16 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete 19 1 DPLL0LTO DPLL0 Lock Timeout 18 1 DPLL1LCKF DPLL1 Lock Fall 25 1 DPLL1LCKR DPLL1 Lock Rise 24 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete 27 1 DPLL1LTO DPLL1 Lock Timeout 26 1 XOSCFAIL0 XOSC 0 Clock Failure Detector 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector 3 1 XOSCRDY0 XOSC 0 Ready 0 1 XOSCRDY1 XOSC 1 Ready 1 1 STATUS Status 0x10 32 read-only n 0x0 0x0 DFLLLCKC DFLL Lock Coarse 11 1 DFLLLCKF DFLL Lock Fine 10 1 DFLLOOB DFLL Out Of Bounds 9 1 DFLLRCS DFLL Reference Clock Stopped 12 1 DFLLRDY DFLL Ready 8 1 DPLL0LCKF DPLL0 Lock Fall 17 1 DPLL0LCKR DPLL0 Lock Rise 16 1 DPLL0LDRTO DPLL0 Loop Divider Ratio Update Complete 19 1 DPLL0TO DPLL0 Timeout 18 1 DPLL1LCKF DPLL1 Lock Fall 25 1 DPLL1LCKR DPLL1 Lock Rise 24 1 DPLL1LDRTO DPLL1 Loop Divider Ratio Update Complete 27 1 DPLL1TO DPLL1 Timeout 26 1 XOSCCKSW0 XOSC 0 Clock Switch 4 1 XOSCCKSW1 XOSC 1 Clock Switch 5 1 XOSCFAIL0 XOSC 0 Clock Failure Detector 2 1 XOSCFAIL1 XOSC 1 Clock Failure Detector 3 1 XOSCRDY0 XOSC 0 Ready 0 1 XOSCRDY1 XOSC 1 Ready 1 1 XOSCCTRL0 External Multipurpose Crystal Oscillator Control 0x14 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 16 1 CFDPRESC Clock Failure Detector Prescaler 24 4 CFDPRESCSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV4 12 MHz 2 DIV8 6 MHz 3 DIV16 3 MHz 4 DIV32 1.5 MHz 5 DIV64 0.75 MHz 6 DIV128 0.3125 MHz 7 ENABLE Oscillator Enable 1 1 ENALC Automatic Loop Control Enable 15 1 IMULT Oscillator Current Multiplier 11 4 IPTAT Oscillator Current Reference 9 2 LOWBUFGAIN Low Buffer Gain Enable 8 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 20 4 STARTUPSelect CYCLE1 31 us 0 CYCLE2 61 us 1 CYCLE1024 31250 us 10 CYCLE2048 62500 us 11 CYCLE4096 125000 us 12 CYCLE8192 250000 us 13 CYCLE16384 500000 us 14 CYCLE32768 1000000 us 15 CYCLE4 122 us 2 CYCLE8 244 us 3 CYCLE16 488 us 4 CYCLE32 977 us 5 CYCLE64 1953 us 6 CYCLE128 3906 us 7 CYCLE256 7813 us 8 CYCLE512 15625 us 9 SWBEN Xosc Clock Switch Enable 17 1 XTALEN Crystal Oscillator Enable 2 1 XOSCCTRL1 External Multipurpose Crystal Oscillator Control 0x18 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 16 1 CFDPRESC Clock Failure Detector Prescaler 24 4 CFDPRESCSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV4 12 MHz 2 DIV8 6 MHz 3 DIV16 3 MHz 4 DIV32 1.5 MHz 5 DIV64 0.75 MHz 6 DIV128 0.3125 MHz 7 ENABLE Oscillator Enable 1 1 ENALC Automatic Loop Control Enable 15 1 IMULT Oscillator Current Multiplier 11 4 IPTAT Oscillator Current Reference 9 2 LOWBUFGAIN Low Buffer Gain Enable 8 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 20 4 STARTUPSelect CYCLE1 31 us 0 CYCLE2 61 us 1 CYCLE1024 31250 us 10 CYCLE2048 62500 us 11 CYCLE4096 125000 us 12 CYCLE8192 250000 us 13 CYCLE16384 500000 us 14 CYCLE32768 1000000 us 15 CYCLE4 122 us 2 CYCLE8 244 us 3 CYCLE16 488 us 4 CYCLE32 977 us 5 CYCLE64 1953 us 6 CYCLE128 3906 us 7 CYCLE256 7813 us 8 CYCLE512 15625 us 9 SWBEN Xosc Clock Switch Enable 17 1 XTALEN Crystal Oscillator Enable 2 1 XOSCCTRL[0] External Multipurpose Crystal Oscillator Control 0x28 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 16 1 CFDPRESC Clock Failure Detector Prescaler 24 4 CFDPRESCSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV4 12 MHz 2 DIV8 6 MHz 3 DIV16 3 MHz 4 DIV32 1.5 MHz 5 DIV64 0.75 MHz 6 DIV128 0.3125 MHz 7 ENABLE Oscillator Enable 1 1 ENALC Automatic Loop Control Enable 15 1 IMULT Oscillator Current Multiplier 11 4 IPTAT Oscillator Current Reference 9 2 LOWBUFGAIN Low Buffer Gain Enable 8 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 20 4 STARTUPSelect CYCLE1 31 us 0 CYCLE2 61 us 1 CYCLE1024 31250 us 10 CYCLE2048 62500 us 11 CYCLE4096 125000 us 12 CYCLE8192 250000 us 13 CYCLE16384 500000 us 14 CYCLE32768 1000000 us 15 CYCLE4 122 us 2 CYCLE8 244 us 3 CYCLE16 488 us 4 CYCLE32 977 us 5 CYCLE64 1953 us 6 CYCLE128 3906 us 7 CYCLE256 7813 us 8 CYCLE512 15625 us 9 SWBEN Xosc Clock Switch Enable 17 1 XTALEN Crystal Oscillator Enable 2 1 XOSCCTRL[1] External Multipurpose Crystal Oscillator Control 0x40 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 16 1 CFDPRESC Clock Failure Detector Prescaler 24 4 CFDPRESCSelect DIV1 48 MHz 0 DIV2 24 MHz 1 DIV4 12 MHz 2 DIV8 6 MHz 3 DIV16 3 MHz 4 DIV32 1.5 MHz 5 DIV64 0.75 MHz 6 DIV128 0.3125 MHz 7 ENABLE Oscillator Enable 1 1 ENALC Automatic Loop Control Enable 15 1 IMULT Oscillator Current Multiplier 11 4 IPTAT Oscillator Current Reference 9 2 LOWBUFGAIN Low Buffer Gain Enable 8 1 ONDEMAND On Demand Control 7 1 RUNSTDBY Run in Standby 6 1 STARTUP Start-Up Time 20 4 STARTUPSelect CYCLE1 31 us 0 CYCLE2 61 us 1 CYCLE1024 31250 us 10 CYCLE2048 62500 us 11 CYCLE4096 125000 us 12 CYCLE8192 250000 us 13 CYCLE16384 500000 us 14 CYCLE32768 1000000 us 15 CYCLE4 122 us 2 CYCLE8 244 us 3 CYCLE16 488 us 4 CYCLE32 977 us 5 CYCLE64 1953 us 6 CYCLE128 3906 us 7 CYCLE256 7813 us 8 CYCLE512 15625 us 9 SWBEN Xosc Clock Switch Enable 17 1 XTALEN Crystal Oscillator Enable 2 1 PAC Peripheral Access Controller PAC 0x0 0x0 0x44 registers n PAC 41 EVCTRL Event control 0x4 8 read-write n 0x0 0x0 ERREO Peripheral acess error event output 0 1 INTENCLR Interrupt enable clear 0x8 8 read-write n 0x0 0x0 ERR Peripheral access error interrupt disable 0 1 INTENSET Interrupt enable set 0x9 8 read-write n 0x0 0x0 ERR Peripheral access error interrupt enable 0 1 INTFLAGA Peripheral interrupt flag status - Bridge A 0x14 32 read-write n 0x0 0x0 EIC_ EIC 10 1 FREQM_ FREQM 11 1 GCLK_ GCLK 7 1 MCLK_ MCLK 2 1 OSC32KCTRL_ OSC32KCTRL 5 1 OSCCTRL_ OSCCTRL 4 1 PAC_ PAC 0 1 PM_ PM 1 1 RSTC_ RSTC 3 1 RTC_ RTC 9 1 SERCOM0_ SERCOM0 12 1 SERCOM1_ SERCOM1 13 1 SUPC_ SUPC 6 1 TC0_ TC0 14 1 TC1_ TC1 15 1 WDT_ WDT 8 1 INTFLAGAHB Bridge interrupt flag status 0x10 32 read-write n 0x0 0x0 BKUPRAM_ BKUPRAM 15 1 FLASH_ FLASH 0 1 FLASH_ALT_ FLASH_ALT 1 1 HPB0_ HPB0 7 1 HPB1_ HPB1 8 1 HPB2_ HPB2 9 1 HPB3_ HPB3 10 1 PUKCC_ PUKCC 11 1 QSPI_ QSPI 14 1 RAMCM4S_ RAMCM4S 3 1 RAMDMACICM_ RAMDMACICM 6 1 RAMDMAWR_ RAMDMAWR 5 1 RAMPPPDSU_ RAMPPPDSU 4 1 SDHC0_ SDHC0 12 1 SEEPROM_ SEEPROM 2 1 INTFLAGB Peripheral interrupt flag status - Bridge B 0x18 32 read-write n 0x0 0x0 CMCC_ CMCC 3 1 DMAC_ DMAC 5 1 DSU_ DSU 1 1 EVSYS_ EVSYS 7 1 HMATRIX_ HMATRIX 6 1 NVMCTRL_ NVMCTRL 2 1 PORT_ PORT 4 1 RAMECC_ RAMECC 16 1 SERCOM2_ SERCOM2 9 1 SERCOM3_ SERCOM3 10 1 TC2_ TC2 13 1 TC3_ TC3 14 1 TCC0_ TCC0 11 1 TCC1_ TCC1 12 1 USB_ USB 0 1 INTFLAGC Peripheral interrupt flag status - Bridge C 0x1C 32 read-write n 0x0 0x0 AC_ AC 8 1 AES_ AES 9 1 CCL_ CCL 14 1 GMAC_ GMAC 2 1 ICM_ ICM 11 1 PDEC_ PDEC 7 1 PUKCC_ PUKCC 12 1 QSPI_ QSPI 13 1 TC4_ TC4 5 1 TC5_ TC5 6 1 TCC2_ TCC2 3 1 TCC3_ TCC3 4 1 TRNG_ TRNG 10 1 INTFLAGD Peripheral interrupt flag status - Bridge D 0x20 32 read-write n 0x0 0x0 ADC0_ ADC0 7 1 ADC1_ ADC1 8 1 DAC_ DAC 9 1 I2S_ I2S 10 1 PCC_ PCC 11 1 SERCOM4_ SERCOM4 0 1 SERCOM5_ SERCOM5 1 1 TCC4_ TCC4 4 1 STATUSA Peripheral write protection status - Bridge A 0x34 32 read-only n 0x0 0x0 EIC_ EIC APB Protect Enable 10 1 FREQM_ FREQM APB Protect Enable 11 1 GCLK_ GCLK APB Protect Enable 7 1 MCLK_ MCLK APB Protect Enable 2 1 OSC32KCTRL_ OSC32KCTRL APB Protect Enable 5 1 OSCCTRL_ OSCCTRL APB Protect Enable 4 1 PAC_ PAC APB Protect Enable 0 1 PM_ PM APB Protect Enable 1 1 RSTC_ RSTC APB Protect Enable 3 1 RTC_ RTC APB Protect Enable 9 1 SERCOM0_ SERCOM0 APB Protect Enable 12 1 SERCOM1_ SERCOM1 APB Protect Enable 13 1 SUPC_ SUPC APB Protect Enable 6 1 TC0_ TC0 APB Protect Enable 14 1 TC1_ TC1 APB Protect Enable 15 1 WDT_ WDT APB Protect Enable 8 1 STATUSB Peripheral write protection status - Bridge B 0x38 32 read-only n 0x0 0x0 CMCC_ CMCC APB Protect Enable 3 1 DMAC_ DMAC APB Protect Enable 5 1 DSU_ DSU APB Protect Enable 1 1 EVSYS_ EVSYS APB Protect Enable 7 1 HMATRIX_ HMATRIX APB Protect Enable 6 1 NVMCTRL_ NVMCTRL APB Protect Enable 2 1 PORT_ PORT APB Protect Enable 4 1 RAMECC_ RAMECC APB Protect Enable 16 1 SERCOM2_ SERCOM2 APB Protect Enable 9 1 SERCOM3_ SERCOM3 APB Protect Enable 10 1 TC2_ TC2 APB Protect Enable 13 1 TC3_ TC3 APB Protect Enable 14 1 TCC0_ TCC0 APB Protect Enable 11 1 TCC1_ TCC1 APB Protect Enable 12 1 USB_ USB APB Protect Enable 0 1 STATUSC Peripheral write protection status - Bridge C 0x3C 32 read-only n 0x0 0x0 AC_ AC APB Protect Enable 8 1 AES_ AES APB Protect Enable 9 1 CCL_ CCL APB Protect Enable 14 1 GMAC_ GMAC APB Protect Enable 2 1 ICM_ ICM APB Protect Enable 11 1 PDEC_ PDEC APB Protect Enable 7 1 PUKCC_ PUKCC APB Protect Enable 12 1 QSPI_ QSPI APB Protect Enable 13 1 TC4_ TC4 APB Protect Enable 5 1 TC5_ TC5 APB Protect Enable 6 1 TCC2_ TCC2 APB Protect Enable 3 1 TCC3_ TCC3 APB Protect Enable 4 1 TRNG_ TRNG APB Protect Enable 10 1 STATUSD Peripheral write protection status - Bridge D 0x40 32 read-only n 0x0 0x0 ADC0_ ADC0 APB Protect Enable 7 1 ADC1_ ADC1 APB Protect Enable 8 1 DAC_ DAC APB Protect Enable 9 1 I2S_ I2S APB Protect Enable 10 1 PCC_ PCC APB Protect Enable 11 1 SERCOM4_ SERCOM4 APB Protect Enable 0 1 SERCOM5_ SERCOM5 APB Protect Enable 1 1 TCC4_ TCC4 APB Protect Enable 4 1 WRCTRL Write control 0x0 32 read-write n 0x0 0x0 KEY Peripheral access control key 16 8 KEYSelect OFF No action 0 CLR Clear protection 1 SET Set protection 2 SETLCK Set and lock protection 3 PERID Peripheral identifier 0 16 PCC Parallel Capture Controller PCC 0x0 0x0 0xE8 registers n PCC 129 IDR Interrupt Disable Register 0x8 32 write-only n 0x0 0x0 DRDY Data Ready Interrupt Disable 0 1 OVRE Overrun Error Interrupt Disable 1 1 IER Interrupt Enable Register 0x4 32 write-only n 0x0 0x0 DRDY Data Ready Interrupt Enable 0 1 OVRE Overrun Error Interrupt Enable 1 1 IMR Interrupt Mask Register 0xC 32 read-only n 0x0 0x0 DRDY Data Ready Interrupt Mask 0 1 OVRE Overrun Error Interrupt Mask 1 1 ISR Interrupt Status Register 0x10 32 read-only n 0x0 0x0 DRDY Data Ready Interrupt Status 0 1 OVRE Overrun Error Interrupt Status 1 1 MR Mode Register 0x0 32 read-write n 0x0 0x0 ALWYS Always Sampling 9 1 CID Clear If Disabled 30 2 DSIZE Data size 4 2 FRSTS First sample 11 1 HALFS Half Sampling 10 1 ISIZE Input Data Size 16 3 PCEN Parallel Capture Enable 0 1 SCALE Scale data 8 1 RHR Reception Holding Register 0x14 32 read-only n 0x0 0x0 RDATA Reception Data 0 32 WPMR Write Protection Mode Register 0xE0 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPSR Write Protection Status Register 0xE4 32 read-only n 0x0 0x0 WPVS Write Protection Violation Source 0 1 WPVSRC Write Protection Violation Status 8 16 PDEC Quadrature Decodeur PDEC 0x0 0x0 0x38 registers n PDEC_OTHER 115 PDEC_MC0 116 PDEC_MC1 117 CC0 Channel n Compare Value 0x20 32 read-write n 0x0 0x0 CC Channel Compare Value 0 16 CC1 Channel n Compare Value 0x24 32 read-write n 0x0 0x0 CC Channel Compare Value 0 16 CCBUF0 Channel Compare Buffer Value 0x30 32 read-write n 0x0 0x0 CCBUF Channel Compare Buffer Value 0 16 CCBUF1 Channel Compare Buffer Value 0x34 32 read-write n 0x0 0x0 CCBUF Channel Compare Buffer Value 0 16 CCBUF[0] Channel Compare Buffer Value 0x60 32 read-write n 0x0 0x0 CCBUF Channel Compare Buffer Value 0 16 CCBUF[1] Channel Compare Buffer Value 0x94 32 read-write n 0x0 0x0 CCBUF Channel Compare Buffer Value 0 16 CC[0] Channel n Compare Value 0x40 32 read-write n 0x0 0x0 CC Channel Compare Value 0 16 CC[1] Channel n Compare Value 0x64 32 read-write n 0x0 0x0 CC Channel Compare Value 0 16 COUNT Counter Value 0x1C 32 read-write n 0x0 0x0 COUNT Counter Value 0 16 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 ANGULAR Angular Counter Length 24 3 CONF PDEC Configuration 8 3 CONFSelect X4 Quadrature decoder direction 0 X4S Secure Quadrature decoder direction 1 X2 Decoder direction 2 X2S Secure decoder direction 3 AUTOC Auto correction mode 4 ENABLE Enable 1 1 MAXCMP Maximum Consecutive Missing Pulses 28 4 MODE Operation Mode 2 2 MODESelect QDEC QDEC operating mode 0 HALL HALL operating mode 1 COUNTER COUNTER operating mode 2 PEREN Period Enable 15 1 PINEN0 PDEC Input From Pin 0 Enable 16 1 PINEN1 PDEC Input From Pin 1 Enable 17 1 PINEN2 PDEC Input From Pin 2 Enable 18 1 PINVEN0 IO Pin 0 Invert Enable 20 1 PINVEN1 IO Pin 1 Invert Enable 21 1 PINVEN2 IO Pin 2 Invert Enable 22 1 RUNSTDBY Run in Standby 6 1 SWAP PDEC Phase A and B Swap 14 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a counter restart or retrigger 1 UPDATE Force update of double buffered registers 2 READSYNC Force a read synchronization of COUNT 3 START Start QDEC/HALL 4 STOP Stop QDEC/HALL 5 LUPD Lock Update 1 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a counter restart or retrigger 1 UPDATE Force update of double buffered registers 2 READSYNC Force a read synchronization of COUNT 3 START Start QDEC/HALL 4 STOP Stop QDEC/HALL 5 LUPD Lock Update 1 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Debug Run Mode 0 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 DIREO Direction Output Event Enable 10 1 ERREO Error Output Event Enable 9 1 EVACT Event Action 0 2 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger on event 1 COUNT Count on event 2 EVEI Event Input Enable 5 3 EVINV Inverted Event Input Enable 2 3 MCEO0 Match Channel 0 Event Output Enable 12 1 MCEO1 Match Channel 1 Event Output Enable 13 1 OVFEO Overflow/Underflow Output Event Enable 8 1 VLCEO Velocity Output Event Enable 11 1 FILTER Filter Value 0x15 8 read-write n 0x0 0x0 FILTER Filter Value 0 8 FILTERBUF Filter Buffer Value 0x19 8 read-write n 0x0 0x0 FILTERBUF Filter Buffer Value 0 8 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 DIR Direction Interrupt Disable 2 1 ERR Error Interrupt Disable 1 1 MC0 Channel 0 Compare Match Disable 4 1 MC1 Channel 1 Compare Match Disable 5 1 OVF Overflow/Underflow Interrupt Disable 0 1 VLC Velocity Interrupt Disable 3 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 DIR Direction Interrupt Enable 2 1 ERR Error Interrupt Enable 1 1 MC0 Channel 0 Compare Match Enable 4 1 MC1 Channel 1 Compare Match Enable 5 1 OVF Overflow/Underflow Interrupt Enable 0 1 VLC Velocity Interrupt Enable 3 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 DIR Direction Change 2 1 ERR Error 1 1 MC0 Channel 0 Compare Match 4 1 MC1 Channel 1 Compare Match 5 1 OVF Overflow/Underflow 0 1 VLC Velocity 3 1 PRESC Prescaler Value 0x14 8 read-write n 0x0 0x0 PRESC Prescaler Value 0 4 PRESCSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV1024 Divide by 1024 10 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV32 Divide by 32 5 DIV64 Divide by 64 6 DIV128 Divide by 128 7 DIV256 Divide by 256 8 DIV512 Divide by 512 9 PRESCBUF Prescaler Buffer Value 0x18 8 read-write n 0x0 0x0 PRESCBUF Prescaler Buffer Value 0 4 PRESCBUFSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV1024 Divide by 1024 10 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV32 Divide by 32 5 DIV64 Divide by 64 6 DIV128 Divide by 128 7 DIV256 Divide by 256 8 DIV512 Divide by 512 9 STATUS Status 0xC 16 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 12 1 CCBUFV1 Compare Channel 1 Buffer Valid 13 1 DIR Direction Status Flag 7 1 FILTERBUFV Filter Buffer Valid 9 1 HERR Hall Error Flag 5 1 IDXERR Index Error Flag 1 1 MPERR Missing Pulse Error flag 2 1 PRESCBUFV Prescaler Buffer Valid 8 1 QERR Quadrature Error Flag 0 1 STOP Stop 6 1 WINERR Window Error Flag 4 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Synchronization Busy 7 1 CC1 Compare Channel 1 Synchronization Busy 8 1 COUNT Count Synchronization Busy 6 1 CTRLB Control B Synchronization Busy 2 1 ENABLE Enable Synchronization Busy 1 1 FILTER Filter Synchronization Busy 5 1 PRESC Prescaler Synchronization Busy 4 1 STATUS Status Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 PM Power Manager PM 0x0 0x0 0x13 registers n PM 0 BKUPCFG Backup Configuration 0xA 8 read-write n 0x0 0x0 BRAMCFG Ram Configuration 0 2 BRAMCFGSelect RET All the backup RAM is retained 0 PARTIAL Only the first 4Kbytes of the backup RAM is retained 1 OFF All the backup RAM is turned OFF 2 CTRLA Control A 0x0 8 read-write n 0x0 0x0 IORET I/O Retention 2 1 HIBCFG Hibernate Configuration 0x9 8 read-write n 0x0 0x0 BRAMCFG Backup Ram Configuration 2 2 BRAMCFGSelect RET All the backup RAM is retained 0 PARTIAL Only the first 4Kbytes of the backup RAM is retained 1 OFF All the backup RAM is turned OFF 2 RAMCFG Ram Configuration 0 2 RAMCFGSelect RET All the system RAM is retained 0 PARTIAL Only the first 32Kbytes of the system RAM is retained 1 OFF All the system RAM is turned OFF 2 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 SLEEPRDY Sleep Mode Entry Ready Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 SLEEPRDY Sleep Mode Entry Ready Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 SLEEPRDY Sleep Mode Entry Ready 0 1 PWSAKDLY Power Switch Acknowledge Delay 0x12 8 read-write n 0x0 0x0 DLYVAL Delay Value 0 7 IGNACK Ignore Acknowledge 7 1 SLEEPCFG Sleep Configuration 0x1 8 read-write n 0x0 0x0 SLEEPMODE Sleep Mode 0 3 SLEEPMODESelect IDLE CPU, AHBx, and APBx clocks are OFF 2 STANDBY All Clocks are OFF 4 HIBERNATE Backup domain is ON as well as some PDRAMs 5 BACKUP Only Backup domain is powered ON 6 OFF All power domains are powered OFF 7 STDBYCFG Standby Configuration 0x8 8 read-write n 0x0 0x0 FASTWKUP Fast Wakeup 4 2 FASTWKUPSelect NO Fast Wakeup is disabled 0 NVM Fast Wakeup is enabled on NVM 1 MAINVREG Fast Wakeup is enabled on the main voltage regulator (MAINVREG) 2 BOTH Fast Wakeup is enabled on both NVM and MAINVREG 3 RAMCFG Ram Configuration 0 2 RAMCFGSelect RET All the system RAM is retained 0 PARTIAL Only the first 32Kbytes of the system RAM is retained 1 OFF All the system RAM is turned OFF 2 PORT Port Module PORT 0x0 0x0 0x100 registers n CTRL Control 0x24 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 DIR Data Direction 0x0 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 DIRCLR Data Direction Clear 0x4 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 DIRSET Data Direction Set 0x8 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 DIRTGL Data Direction Toggle 0xC 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 EVCTRL Event Input Control 0x2C 32 read-write n 0x0 0x0 EVACT0 PORT Event Action 0 5 2 EVACT0Select OUT Event output to pin 0x0 SET Set output register of pin on event 0x1 CLR Clear output register of pin on event 0x2 TGL Toggle output register of pin on event 0x3 EVACT1 PORT Event Action 1 13 2 EVACT2 PORT Event Action 2 21 2 EVACT3 PORT Event Action 3 29 2 PID0 PORT Event Pin Identifier 0 0 5 PID1 PORT Event Pin Identifier 1 8 5 PID2 PORT Event Pin Identifier 2 16 5 PID3 PORT Event Pin Identifier 3 24 5 PORTEI0 PORT Event Input Enable 0 7 1 PORTEI1 PORT Event Input Enable 1 15 1 PORTEI2 PORT Event Input Enable 2 23 1 PORTEI3 PORT Event Input Enable 3 31 1 GROUP[0]-CTRL Control 0x24 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 GROUP[0]-DIR Data Direction 0x0 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 GROUP[0]-DIRCLR Data Direction Clear 0x4 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 GROUP[0]-DIRSET Data Direction Set 0x8 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 GROUP[0]-DIRTGL Data Direction Toggle 0xC 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 GROUP[0]-EVCTRL Event Input Control 0x2C 32 read-write n 0x0 0x0 EVACT0 PORT Event Action 0 5 2 EVACT0Select OUT Event output to pin 0 SET Set output register of pin on event 1 CLR Clear output register of pin on event 2 TGL Toggle output register of pin on event 3 EVACT1 PORT Event Action 1 13 2 EVACT2 PORT Event Action 2 21 2 EVACT3 PORT Event Action 3 29 2 PID0 PORT Event Pin Identifier 0 0 5 PID1 PORT Event Pin Identifier 1 8 5 PID2 PORT Event Pin Identifier 2 16 5 PID3 PORT Event Pin Identifier 3 24 5 PORTEI0 PORT Event Input Enable 0 7 1 PORTEI1 PORT Event Input Enable 1 15 1 PORTEI2 PORT Event Input Enable 2 23 1 PORTEI3 PORT Event Input Enable 3 31 1 GROUP[0]-IN Data Input Value 0x20 32 read-only n 0x0 0x0 IN PORT Data Input Value 0 32 GROUP[0]-OUT Data Output Value 0x10 32 read-write n 0x0 0x0 OUT PORT Data Output Value 0 32 GROUP[0]-OUTCLR Data Output Value Clear 0x14 32 read-write n 0x0 0x0 OUTCLR PORT Data Output Value Clear 0 32 GROUP[0]-OUTSET Data Output Value Set 0x18 32 read-write n 0x0 0x0 OUTSET PORT Data Output Value Set 0 32 GROUP[0]-OUTTGL Data Output Value Toggle 0x1C 32 read-write n 0x0 0x0 OUTTGL PORT Data Output Value Toggle 0 32 GROUP[0]-PINCFG[0] Pin Configuration 0x80 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[10] Pin Configuration 0x337 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[11] Pin Configuration 0x382 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[12] Pin Configuration 0x3CE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[13] Pin Configuration 0x41B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[14] Pin Configuration 0x469 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[15] Pin Configuration 0x4B8 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[16] Pin Configuration 0x508 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[17] Pin Configuration 0x559 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[18] Pin Configuration 0x5AB 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[19] Pin Configuration 0x5FE 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[1] Pin Configuration 0xC1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[20] Pin Configuration 0x652 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[21] Pin Configuration 0x6A7 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[22] Pin Configuration 0x6FD 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[23] Pin Configuration 0x754 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[24] Pin Configuration 0x7AC 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[25] Pin Configuration 0x805 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[26] Pin Configuration 0x85F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[27] Pin Configuration 0x8BA 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[28] Pin Configuration 0x916 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[29] Pin Configuration 0x973 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[2] Pin Configuration 0x103 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[30] Pin Configuration 0x9D1 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[31] Pin Configuration 0xA30 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[3] Pin Configuration 0x146 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[4] Pin Configuration 0x18A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[5] Pin Configuration 0x1CF 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[6] Pin Configuration 0x215 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[7] Pin Configuration 0x25C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[8] Pin Configuration 0x2A4 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PINCFG[9] Pin Configuration 0x2ED 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[0]-PMUX[0] Peripheral Multiplexing 0x60 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[10] Peripheral Multiplexing 0x277 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[11] Peripheral Multiplexing 0x2B2 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[12] Peripheral Multiplexing 0x2EE 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[13] Peripheral Multiplexing 0x32B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[14] Peripheral Multiplexing 0x369 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[15] Peripheral Multiplexing 0x3A8 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[1] Peripheral Multiplexing 0x91 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[2] Peripheral Multiplexing 0xC3 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[3] Peripheral Multiplexing 0xF6 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[4] Peripheral Multiplexing 0x12A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[5] Peripheral Multiplexing 0x15F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[6] Peripheral Multiplexing 0x195 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[7] Peripheral Multiplexing 0x1CC 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[8] Peripheral Multiplexing 0x204 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-PMUX[9] Peripheral Multiplexing 0x23D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[0]-WRCONFIG Write Configuration 0x28 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 GROUP[1]-GROUP[0]-CTRL Control 0xA4 32 read-write n 0x0 0x0 SAMPLING Input Sampling Mode 0 32 GROUP[1]-GROUP[0]-DIR Data Direction 0x80 32 read-write n 0x0 0x0 DIR Port Data Direction 0 32 GROUP[1]-GROUP[0]-DIRCLR Data Direction Clear 0x84 32 read-write n 0x0 0x0 DIRCLR Port Data Direction Clear 0 32 GROUP[1]-GROUP[0]-DIRSET Data Direction Set 0x88 32 read-write n 0x0 0x0 DIRSET Port Data Direction Set 0 32 GROUP[1]-GROUP[0]-DIRTGL Data Direction Toggle 0x8C 32 read-write n 0x0 0x0 DIRTGL Port Data Direction Toggle 0 32 GROUP[1]-GROUP[0]-EVCTRL Event Input Control 0xAC 32 read-write n 0x0 0x0 EVACT0 PORT Event Action 0 5 2 EVACT0Select OUT Event output to pin 0 SET Set output register of pin on event 1 CLR Clear output register of pin on event 2 TGL Toggle output register of pin on event 3 EVACT1 PORT Event Action 1 13 2 EVACT2 PORT Event Action 2 21 2 EVACT3 PORT Event Action 3 29 2 PID0 PORT Event Pin Identifier 0 0 5 PID1 PORT Event Pin Identifier 1 8 5 PID2 PORT Event Pin Identifier 2 16 5 PID3 PORT Event Pin Identifier 3 24 5 PORTEI0 PORT Event Input Enable 0 7 1 PORTEI1 PORT Event Input Enable 1 15 1 PORTEI2 PORT Event Input Enable 2 23 1 PORTEI3 PORT Event Input Enable 3 31 1 GROUP[1]-GROUP[0]-IN Data Input Value 0xA0 32 read-only n 0x0 0x0 IN PORT Data Input Value 0 32 GROUP[1]-GROUP[0]-OUT Data Output Value 0x90 32 read-write n 0x0 0x0 OUT PORT Data Output Value 0 32 GROUP[1]-GROUP[0]-OUTCLR Data Output Value Clear 0x94 32 read-write n 0x0 0x0 OUTCLR PORT Data Output Value Clear 0 32 GROUP[1]-GROUP[0]-OUTSET Data Output Value Set 0x98 32 read-write n 0x0 0x0 OUTSET PORT Data Output Value Set 0 32 GROUP[1]-GROUP[0]-OUTTGL Data Output Value Toggle 0x9C 32 read-write n 0x0 0x0 OUTTGL PORT Data Output Value Toggle 0 32 GROUP[1]-GROUP[0]-PINCFG[31] Pin Configuration 0xAB0 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 GROUP[1]-GROUP[0]-PMUX[15] Peripheral Multiplexing 0x428 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 GROUP[1]-GROUP[0]-WRCONFIG Write Configuration 0xA8 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 IN Data Input Value 0x20 32 read-only n 0x0 0x0 IN PORT Data Input Value 0 32 OUT Data Output Value 0x10 32 read-write n 0x0 0x0 OUT PORT Data Output Value 0 32 OUTCLR Data Output Value Clear 0x14 32 read-write n 0x0 0x0 OUTCLR PORT Data Output Value Clear 0 32 OUTSET Data Output Value Set 0x18 32 read-write n 0x0 0x0 OUTSET PORT Data Output Value Set 0 32 OUTTGL Data Output Value Toggle 0x1C 32 read-write n 0x0 0x0 OUTTGL PORT Data Output Value Toggle 0 32 PINCFG0 Pin Configuration 0x40 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG1 Pin Configuration 0x41 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG10 Pin Configuration 0x4A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG11 Pin Configuration 0x4B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG12 Pin Configuration 0x4C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG13 Pin Configuration 0x4D 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG14 Pin Configuration 0x4E 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG15 Pin Configuration 0x4F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG16 Pin Configuration 0x50 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG17 Pin Configuration 0x51 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG18 Pin Configuration 0x52 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG19 Pin Configuration 0x53 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG2 Pin Configuration 0x42 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG20 Pin Configuration 0x54 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG21 Pin Configuration 0x55 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG22 Pin Configuration 0x56 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG23 Pin Configuration 0x57 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG24 Pin Configuration 0x58 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG25 Pin Configuration 0x59 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG26 Pin Configuration 0x5A 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG27 Pin Configuration 0x5B 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG28 Pin Configuration 0x5C 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG29 Pin Configuration 0x5D 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG3 Pin Configuration 0x43 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG30 Pin Configuration 0x5E 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG31 Pin Configuration 0x5F 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG4 Pin Configuration 0x44 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG5 Pin Configuration 0x45 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG6 Pin Configuration 0x46 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG7 Pin Configuration 0x47 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG8 Pin Configuration 0x48 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PINCFG9 Pin Configuration 0x49 8 read-write n 0x0 0x0 DRVSTR Output Driver Strength Selection 6 1 INEN Input Enable 1 1 PMUXEN Peripheral Multiplexer Enable 0 1 PULLEN Pull Enable 2 1 PMUX0 Peripheral Multiplexing 0x30 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX1 Peripheral Multiplexing 0x31 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX10 Peripheral Multiplexing 0x3A 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX11 Peripheral Multiplexing 0x3B 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX12 Peripheral Multiplexing 0x3C 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX13 Peripheral Multiplexing 0x3D 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX14 Peripheral Multiplexing 0x3E 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX15 Peripheral Multiplexing 0x3F 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX2 Peripheral Multiplexing 0x32 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX3 Peripheral Multiplexing 0x33 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX4 Peripheral Multiplexing 0x34 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX5 Peripheral Multiplexing 0x35 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX6 Peripheral Multiplexing 0x36 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX7 Peripheral Multiplexing 0x37 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX8 Peripheral Multiplexing 0x38 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUX9 Peripheral Multiplexing 0x39 8 read-write n 0x0 0x0 PMUXE Peripheral Multiplexing for Even-Numbered Pin 0 4 PMUXESelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD PMUXO Peripheral Multiplexing for Odd-Numbered Pin 4 4 PMUXOSelect A Peripheral function A selected 0x0 B Peripheral function B selected 0x1 C Peripheral function C selected 0x2 D Peripheral function D selected 0x3 E Peripheral function E selected 0x4 F Peripheral function F selected 0x5 G Peripheral function G selected 0x6 H Peripheral function H selected 0x7 I Peripheral function I selected 0x8 J Peripheral function J selected 0x9 K Peripheral function K selected 0xA L Peripheral function L selected 0xB M Peripheral function M selected 0xC N Peripheral function N selected 0xD WRCONFIG Write Configuration 0x28 32 write-only n 0x0 0x0 DRVSTR Output Driver Strength Selection 22 1 HWSEL Half-Word Select 31 1 INEN Input Enable 17 1 PINMASK Pin Mask for Multiple Pin Configuration 0 16 PMUX Peripheral Multiplexing 24 4 PMUXEN Peripheral Multiplexer Enable 16 1 PULLEN Pull Enable 18 1 WRPINCFG Write PINCFG 30 1 WRPMUX Write PMUX 28 1 QSPI Quad SPI interface QSPI 0x0 0x0 0x48 registers n QSPI 134 BAUD Baud Rate 0x8 32 read-write n 0x0 0x0 BAUD Serial Clock Baud Rate 8 8 CPHA Clock Phase 1 1 CPOL Clock Polarity 0 1 DLYBS Delay Before SCK 16 8 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LASTXFER Last Transfer 24 1 SWRST Software Reset 0 1 CTRLB Control B 0x4 32 read-write n 0x0 0x0 CSMODE Chip Select Mode 4 2 CSMODESelect NORELOAD The chip select is deasserted if TD has not been reloaded before the end of the current transfer. 0 LASTXFER The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. 1 SYSTEMATICALLY The chip select is deasserted systematically after each transfer. 2 DATALEN Data Length 8 4 DATALENSelect 8BITS 8-bits transfer 0 9BITS 9 bits transfer 1 10BITS 10-bits transfer 2 11BITS 11-bits transfer 3 12BITS 12-bits transfer 4 13BITS 13-bits transfer 5 14BITS 14-bits transfer 6 15BITS 15-bits transfer 7 16BITS 16-bits transfer 8 DLYBCT Delay Between Consecutive Transfers 16 8 DLYCS Minimum Inactive CS Delay 24 8 LOOPEN Local Loopback Enable 1 1 MODE Serial Memory Mode 0 1 MODESelect SPI SPI operating mode 0 MEMORY Serial Memory operating mode 1 SMEMREG Serial Memory reg 3 1 WDRBT Wait Data Read Before Transfer 2 1 INSTRADDR Instruction Address 0x30 32 read-write n 0x0 0x0 ADDR Instruction Address 0 32 INSTRCTRL Instruction Code 0x34 32 read-write n 0x0 0x0 INSTR Instruction Code 0 8 OPTCODE Option Code 16 8 INSTRFRAME Instruction Frame 0x38 32 read-write n 0x0 0x0 ADDREN Address Enable 5 1 ADDRLEN Address Length 10 1 ADDRLENSelect 24BITS 24-bits address length 0 32BITS 32-bits address length 1 CRMODE Continuous Read Mode 14 1 DATAEN Data Enable 7 1 DDREN Double Data Rate Enable 15 1 DUMMYLEN Dummy Cycles Length 16 5 INSTREN Instruction Enable 4 1 OPTCODEEN Option Enable 6 1 OPTCODELEN Option Code Length 8 2 OPTCODELENSelect 1BIT 1-bit length option code 0 2BITS 2-bits length option code 1 4BITS 4-bits length option code 2 8BITS 8-bits length option code 3 TFRTYPE Data Transfer Type 12 2 TFRTYPESelect READ Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. 0 READMEMORY Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. 1 WRITE Write transfer into the serial memory.Scrambling is not performed. 2 WRITEMEMORY Write data transfer into the serial memory.If enabled, scrambling is performed. 3 WIDTH Instruction Code, Address, Option Code and Data Width 0 3 WIDTHSelect SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI 0 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI 1 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI 2 DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI 3 QUAD_IO Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI 4 DUAL_CMD Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI 5 QUAD_CMD Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI 6 INTENCLR Interrupt Enable Clear 0x14 32 read-write n 0x0 0x0 CSRISE Chip Select Rise Interrupt Disable 8 1 DRE Transmit Data Register Empty Interrupt Disable 1 1 ERROR Overrun Error Interrupt Disable 3 1 INSTREND Instruction End Interrupt Disable 10 1 RXC Receive Data Register Full Interrupt Disable 0 1 TXC Transmission Complete Interrupt Disable 2 1 INTENSET Interrupt Enable Set 0x18 32 read-write n 0x0 0x0 CSRISE Chip Select Rise Interrupt Enable 8 1 DRE Transmit Data Register Empty Interrupt Enable 1 1 ERROR Overrun Error Interrupt Enable 3 1 INSTREND Instruction End Interrupt Enable 10 1 RXC Receive Data Register Full Interrupt Enable 0 1 TXC Transmission Complete Interrupt Enable 2 1 INTFLAG Interrupt Flag Status and Clear 0x1C 32 read-write n 0x0 0x0 CSRISE Chip Select Rise 8 1 DRE Transmit Data Register Empty 1 1 ERROR Overrun Error 3 1 INSTREND Instruction End 10 1 RXC Receive Data Register Full 0 1 TXC Transmission Complete 2 1 RXDATA Receive Data 0xC 32 read-only n 0x0 0x0 DATA Receive Data 0 16 SCRAMBCTRL Scrambling Mode 0x40 32 read-write n 0x0 0x0 ENABLE Scrambling/Unscrambling Enable 0 1 RANDOMDIS Scrambling/Unscrambling Random Value Disable 1 1 SCRAMBKEY Scrambling Key 0x44 32 write-only n 0x0 0x0 KEY Scrambling User Key 0 32 STATUS Status Register 0x20 32 read-only n 0x0 0x0 CSSTATUS Chip Select 9 1 ENABLE Enable 1 1 TXDATA Transmit Data 0x10 32 write-only n 0x0 0x0 DATA Transmit Data 0 16 RAMECC RAM ECC RAMECC 0x0 0x0 0x10 registers n RAMECC 45 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 ECCDIS ECC Disable 0 1 ECCELOG ECC Error Log 1 1 ERRADDR Error Address 0x4 32 read-only n 0x0 0x0 ERRADDR Error Address 0 17 INTENCLR Interrupt Enable Clear 0x0 8 read-write n 0x0 0x0 DUALE Dual Bit ECC Error Interrupt Enable Clear 1 1 SINGLEE Single Bit ECC Error Interrupt Enable Clear 0 1 INTENSET Interrupt Enable Set 0x1 8 read-write n 0x0 0x0 DUALE Dual Bit ECC Error Interrupt Enable Set 1 1 SINGLEE Single Bit ECC Error Interrupt Enable Set 0 1 INTFLAG Interrupt Flag 0x2 8 read-write n 0x0 0x0 DUALE Dual Bit ECC Error Interrupt 1 1 SINGLEE Single Bit ECC Error Interrupt 0 1 STATUS Status 0x3 8 read-only n 0x0 0x0 ECCDIS ECC Disable 0 1 RSTC Reset Controller RSTC 0x0 0x0 0x3 registers n BKUPEXIT Backup Exit Source 0x2 8 read-only n 0x0 0x0 BBPS Battery Backup Power Switch 2 1 HIB Hibernate 7 1 RTC Real Timer Counter Interrupt 1 1 RCAUSE Reset Cause 0x0 8 read-only n 0x0 0x0 BACKUP Backup Reset 7 1 BODCORE Brown Out CORE Detector Reset 1 1 BODVDD Brown Out VDD Detector Reset 2 1 EXT External Reset 4 1 NVM NVM Reset 3 1 POR Power On Reset 0 1 SYST System Reset Request 6 1 WDT Watchdog Reset 5 1 RTC Real-Time Counter RTC 0x0 0x0 0xA0 registers n RTC 11 ALARM0 MODE2_ALARM Alarm n Value 0x20 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 ALARM1 MODE2_ALARM Alarm n Value 0x28 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0x00 PM Afternoon hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 BKUP0 Backup 0x80 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP1 Backup 0x84 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP2 Backup 0x88 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP3 Backup 0x8C 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP4 Backup 0x90 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP5 Backup 0x94 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP6 Backup 0x98 32 read-write n 0x0 0x0 BKUP Backup 0 32 BKUP7 Backup 0x9C 32 read-write n 0x0 0x0 BKUP Backup 0 32 CLOCK MODE2 Clock Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x00 PM PM when CLKREP in 12-hour 0x10 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 COMP0 MODE1 Compare n Value 0x20 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COMP1 MODE1 Compare n Value 0x22 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COMP2 MODE1 Compare n Value 0x24 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COMP3 MODE1 Compare n Value 0x26 16 read-write n 0x0 0x0 COMP Compare Value 0 16 COUNT MODE1 Counter Value 0x18 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 CTRLA MODE2 Control A 0x0 16 read-write n 0x0 0x0 BKTRST BKUP Registers Reset On Tamper Enable 13 1 CLKREP Clock Representation 6 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 GPTRST GP Registers Reset On Tamper Enable 14 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0x0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 0x1 DIV2 CLK_RTC_CNT = GCLK_RTC/2 0x2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 0x3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 0x4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 0x5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 0x6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 0x7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 0x8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 0x9 DIV512 CLK_RTC_CNT = GCLK_RTC/512 0xA DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 0xB SWRST Software Reset 0 1 CTRLB MODE2 Control B 0x2 16 read-write n 0x0 0x0 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0x0 DIV4 CLK_RTC_OUT = CLK_RTC/4 0x1 DIV8 CLK_RTC_OUT = CLK_RTC/8 0x2 DIV16 CLK_RTC_OUT = CLK_RTC/16 0x3 DIV32 CLK_RTC_OUT = CLK_RTC/32 0x4 DIV64 CLK_RTC_OUT = CLK_RTC/64 0x5 DIV128 CLK_RTC_OUT = CLK_RTC/128 0x6 DIV256 CLK_RTC_OUT = CLK_RTC/256 0x7 DEBASYNC Debouncer Asynchronous Enable 5 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0x0 DIV4 CLK_RTC_DEB = CLK_RTC/4 0x1 DIV8 CLK_RTC_DEB = CLK_RTC/8 0x2 DIV16 CLK_RTC_DEB = CLK_RTC/16 0x3 DIV32 CLK_RTC_DEB = CLK_RTC/32 0x4 DIV64 CLK_RTC_DEB = CLK_RTC/64 0x5 DIV128 CLK_RTC_DEB = CLK_RTC/128 0x6 DIV256 CLK_RTC_DEB = CLK_RTC/256 0x7 DEBMAJ Debouncer Majority Enable 4 1 DMAEN DMA Enable 7 1 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 RTCOUT RTC Output Enable 6 1 DBGCTRL Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 EVCTRL MODE2 Event Control 0x4 32 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 ALARMEO1 Alarm 1 Event Output Enable 9 1 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 CMPEO2 Compare 2 Event Output Enable 10 1 CMPEO3 Compare 3 Event Output Enable 11 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 TAMPEREO Tamper Event Output Enable 14 1 TAMPEVEI Tamper Event Input Enable 16 1 FREQCORR Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 GP0 General Purpose 0x40 32 read-write n 0x0 0x0 GP General Purpose 0 32 GP1 General Purpose 0x44 32 read-write n 0x0 0x0 GP General Purpose 0 32 GP2 General Purpose 0x48 32 read-write n 0x0 0x0 GP General Purpose 0 32 GP3 General Purpose 0x4C 32 read-write n 0x0 0x0 GP General Purpose 0 32 INTENCLR MODE2 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 ALARM1 Alarm 1 Interrupt Enable 9 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 CMP2 Compare 2 Interrupt Enable 10 1 CMP3 Compare 3 Interrupt Enable 11 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 TAMPER Tamper Enable 14 1 INTENSET MODE2 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 ALARM1 Alarm 1 Interrupt Enable 9 1 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 CMP2 Compare 2 Interrupt Enable 10 1 CMP3 Compare 3 Interrupt Enable 11 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 TAMPER Tamper Enable 14 1 INTFLAG MODE2 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 ALARM1 Alarm 1 9 1 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 CMP2 Compare 2 10 1 CMP3 Compare 3 11 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 TAMPER Tamper 14 1 MASK0 MODE2_ALARM Alarm n Mask 0x24 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MASK1 MODE2_ALARM Alarm n Mask 0x2C 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0x0 SS Match seconds only 0x1 MMSS Match seconds and minutes only 0x2 HHMMSS Match seconds, minutes, and hours only 0x3 DDHHMMSS Match seconds, minutes, hours, and days only 0x4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 0x5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 0x6 MODE0 - BKUP[0] 32-bit Counter with Single 32-bit Compare - - Backup 0x100 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[1] 32-bit Counter with Single 32-bit Compare - - Backup 0x184 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[2] 32-bit Counter with Single 32-bit Compare - - Backup 0x20C 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[3] 32-bit Counter with Single 32-bit Compare - - Backup 0x298 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[4] 32-bit Counter with Single 32-bit Compare - - Backup 0x328 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[5] 32-bit Counter with Single 32-bit Compare - - Backup 0x3BC 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[6] 32-bit Counter with Single 32-bit Compare - - Backup 0x454 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - BKUP[7] 32-bit Counter with Single 32-bit Compare - - Backup 0x4F0 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE0 - COMP[0] 32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value 0x40 32 read-write n 0x0 0x0 COMP Compare Value 0 32 MODE0 - COMP[1] 32-bit Counter with Single 32-bit Compare - - MODE0 Compare n Value 0x64 32 read-write n 0x0 0x0 COMP Compare Value 0 32 MODE0 - COUNT 32-bit Counter with Single 32-bit Compare - - MODE0 Counter Value 0x18 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 MODE0 - CTRLA 32-bit Counter with Single 32-bit Compare - - MODE0 Control A 0x0 16 read-write n 0x0 0x0 BKTRST BKUP Registers Reset On Tamper Enable 13 1 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 GPTRST GP Registers Reset On Tamper Enable 14 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 1 DIV512 CLK_RTC_CNT = GCLK_RTC/512 10 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 11 DIV2 CLK_RTC_CNT = GCLK_RTC/2 2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 9 SWRST Software Reset 0 1 MODE0 - CTRLB 32-bit Counter with Single 32-bit Compare - - MODE0 Control B 0x2 16 read-write n 0x0 0x0 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0 DIV4 CLK_RTC_OUT = CLK_RTC/4 1 DIV8 CLK_RTC_OUT = CLK_RTC/8 2 DIV16 CLK_RTC_OUT = CLK_RTC/16 3 DIV32 CLK_RTC_OUT = CLK_RTC/32 4 DIV64 CLK_RTC_OUT = CLK_RTC/64 5 DIV128 CLK_RTC_OUT = CLK_RTC/128 6 DIV256 CLK_RTC_OUT = CLK_RTC/256 7 DEBASYNC Debouncer Asynchronous Enable 5 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0 DIV4 CLK_RTC_DEB = CLK_RTC/4 1 DIV8 CLK_RTC_DEB = CLK_RTC/8 2 DIV16 CLK_RTC_DEB = CLK_RTC/16 3 DIV32 CLK_RTC_DEB = CLK_RTC/32 4 DIV64 CLK_RTC_DEB = CLK_RTC/64 5 DIV128 CLK_RTC_DEB = CLK_RTC/128 6 DIV256 CLK_RTC_DEB = CLK_RTC/256 7 DEBMAJ Debouncer Majority Enable 4 1 DMAEN DMA Enable 7 1 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 RTCOUT RTC Output Enable 6 1 MODE0 - DBGCTRL 32-bit Counter with Single 32-bit Compare - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE0 - EVCTRL 32-bit Counter with Single 32-bit Compare - - MODE0 Event Control 0x4 32 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 TAMPEREO Tamper Event Output Enable 14 1 TAMPEVEI Tamper Event Input Enable 16 1 MODE0 - FREQCORR 32-bit Counter with Single 32-bit Compare - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE0 - GP[0] 32-bit Counter with Single 32-bit Compare - - General Purpose 0x80 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE0 - GP[1] 32-bit Counter with Single 32-bit Compare - - General Purpose 0xC4 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE0 - GP[2] 32-bit Counter with Single 32-bit Compare - - General Purpose 0x10C 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE0 - GP[3] 32-bit Counter with Single 32-bit Compare - - General Purpose 0x158 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE0 - INTENCLR 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 TAMPER Tamper Enable 14 1 MODE0 - INTENSET 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 TAMPER Tamper Enable 14 1 MODE0 - INTFLAG 32-bit Counter with Single 32-bit Compare - - MODE0 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 TAMPER Tamper 14 1 MODE0 - SYNCBUSY 32-bit Counter with Single 32-bit Compare - - MODE0 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COUNT COUNT Register Busy 3 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 SWRST Software Reset Busy 0 1 MODE0 - TAMPCTRL 32-bit Counter with Single 32-bit Compare - - Tamper Control 0x60 32 read-write n 0x0 0x0 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN0 to OUT 3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN1 to OUT 3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN2 to OUT 3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN3 to OUT 3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN4 to OUT 3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 MODE0 - TAMPID 32-bit Counter with Single 32-bit Compare - - Tamper ID 0x68 32 read-write n 0x0 0x0 TAMPEVT Tamper Event Detected 31 1 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 MODE0 - TIMESTAMP 32-bit Counter with Single 32-bit Compare - - MODE0 Timestamp 0x64 32 read-only n 0x0 0x0 COUNT Count Timestamp Value 0 32 MODE1 - BKUP[0] 16-bit Counter with Two 16-bit Compares - - Backup 0x100 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[1] 16-bit Counter with Two 16-bit Compares - - Backup 0x184 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[2] 16-bit Counter with Two 16-bit Compares - - Backup 0x20C 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[3] 16-bit Counter with Two 16-bit Compares - - Backup 0x298 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[4] 16-bit Counter with Two 16-bit Compares - - Backup 0x328 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[5] 16-bit Counter with Two 16-bit Compares - - Backup 0x3BC 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[6] 16-bit Counter with Two 16-bit Compares - - Backup 0x454 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - BKUP[7] 16-bit Counter with Two 16-bit Compares - - Backup 0x4F0 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE1 - COMP[0] 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x40 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COMP[1] 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x62 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COMP[2] 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0x86 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COMP[3] 16-bit Counter with Two 16-bit Compares - - MODE1 Compare n Value 0xAC 16 read-write n 0x0 0x0 COMP Compare Value 0 16 MODE1 - COUNT 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Value 0x18 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 MODE1 - CTRLA 16-bit Counter with Two 16-bit Compares - - MODE1 Control A 0x0 16 read-write n 0x0 0x0 BKTRST BKUP Registers Reset On Tamper Enable 13 1 COUNTSYNC Count Read Synchronization Enable 15 1 ENABLE Enable 1 1 GPTRST GP Registers Reset On Tamper Enable 14 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 1 DIV512 CLK_RTC_CNT = GCLK_RTC/512 10 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 11 DIV2 CLK_RTC_CNT = GCLK_RTC/2 2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 9 SWRST Software Reset 0 1 MODE1 - CTRLB 16-bit Counter with Two 16-bit Compares - - MODE1 Control B 0x2 16 read-write n 0x0 0x0 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0 DIV4 CLK_RTC_OUT = CLK_RTC/4 1 DIV8 CLK_RTC_OUT = CLK_RTC/8 2 DIV16 CLK_RTC_OUT = CLK_RTC/16 3 DIV32 CLK_RTC_OUT = CLK_RTC/32 4 DIV64 CLK_RTC_OUT = CLK_RTC/64 5 DIV128 CLK_RTC_OUT = CLK_RTC/128 6 DIV256 CLK_RTC_OUT = CLK_RTC/256 7 DEBASYNC Debouncer Asynchronous Enable 5 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0 DIV4 CLK_RTC_DEB = CLK_RTC/4 1 DIV8 CLK_RTC_DEB = CLK_RTC/8 2 DIV16 CLK_RTC_DEB = CLK_RTC/16 3 DIV32 CLK_RTC_DEB = CLK_RTC/32 4 DIV64 CLK_RTC_DEB = CLK_RTC/64 5 DIV128 CLK_RTC_DEB = CLK_RTC/128 6 DIV256 CLK_RTC_DEB = CLK_RTC/256 7 DEBMAJ Debouncer Majority Enable 4 1 DMAEN DMA Enable 7 1 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 RTCOUT RTC Output Enable 6 1 MODE1 - DBGCTRL 16-bit Counter with Two 16-bit Compares - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE1 - EVCTRL 16-bit Counter with Two 16-bit Compares - - MODE1 Event Control 0x4 32 read-write n 0x0 0x0 CMPEO0 Compare 0 Event Output Enable 8 1 CMPEO1 Compare 1 Event Output Enable 9 1 CMPEO2 Compare 2 Event Output Enable 10 1 CMPEO3 Compare 3 Event Output Enable 11 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 TAMPEREO Tamper Event Output Enable 14 1 TAMPEVEI Tamper Event Input Enable 16 1 MODE1 - FREQCORR 16-bit Counter with Two 16-bit Compares - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE1 - GP[0] 16-bit Counter with Two 16-bit Compares - - General Purpose 0x80 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE1 - GP[1] 16-bit Counter with Two 16-bit Compares - - General Purpose 0xC4 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE1 - GP[2] 16-bit Counter with Two 16-bit Compares - - General Purpose 0x10C 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE1 - GP[3] 16-bit Counter with Two 16-bit Compares - - General Purpose 0x158 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE1 - INTENCLR 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 CMP2 Compare 2 Interrupt Enable 10 1 CMP3 Compare 3 Interrupt Enable 11 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 TAMPER Tamper Enable 14 1 MODE1 - INTENSET 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 CMP0 Compare 0 Interrupt Enable 8 1 CMP1 Compare 1 Interrupt Enable 9 1 CMP2 Compare 2 Interrupt Enable 10 1 CMP3 Compare 3 Interrupt Enable 11 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 TAMPER Tamper Enable 14 1 MODE1 - INTFLAG 16-bit Counter with Two 16-bit Compares - - MODE1 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 CMP0 Compare 0 8 1 CMP1 Compare 1 9 1 CMP2 Compare 2 10 1 CMP3 Compare 3 11 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 TAMPER Tamper 14 1 MODE1 - PER 16-bit Counter with Two 16-bit Compares - - MODE1 Counter Period 0x1C 16 read-write n 0x0 0x0 PER Counter Period 0 16 MODE1 - SYNCBUSY 16-bit Counter with Two 16-bit Compares - - MODE1 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COMP2 COMP 2 Register Busy 7 1 COMP3 COMP 3 Register Busy 8 1 COUNT COUNT Register Busy 3 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 PER PER Register Busy 4 1 SWRST Software Reset Bit Busy 0 1 MODE1 - TAMPCTRL 16-bit Counter with Two 16-bit Compares - - Tamper Control 0x60 32 read-write n 0x0 0x0 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN0 to OUT 3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN1 to OUT 3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN2 to OUT 3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN3 to OUT 3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN4 to OUT 3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 MODE1 - TAMPID 16-bit Counter with Two 16-bit Compares - - Tamper ID 0x68 32 read-write n 0x0 0x0 TAMPEVT Tamper Event Detected 31 1 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 MODE1 - TIMESTAMP 16-bit Counter with Two 16-bit Compares - - MODE1 Timestamp 0x64 32 read-only n 0x0 0x0 COUNT Count Timestamp Value 0 16 MODE2 - ALARM0 Clock/Calendar with Alarm - - MODE2_ALARM Alarm n Value 0x20 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0 PM Afternoon hour 16 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - ALARM1 Clock/Calendar with Alarm - - MODE2_ALARM Alarm n Value 0x28 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM Morning hour 0 PM Afternoon hour 16 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - BKUP[0] Clock/Calendar with Alarm - - Backup 0x100 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[1] Clock/Calendar with Alarm - - Backup 0x184 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[2] Clock/Calendar with Alarm - - Backup 0x20C 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[3] Clock/Calendar with Alarm - - Backup 0x298 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[4] Clock/Calendar with Alarm - - Backup 0x328 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[5] Clock/Calendar with Alarm - - Backup 0x3BC 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[6] Clock/Calendar with Alarm - - Backup 0x454 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - BKUP[7] Clock/Calendar with Alarm - - Backup 0x4F0 32 read-write n 0x0 0x0 BKUP Backup 0 32 MODE2 - CLOCK Clock/Calendar with Alarm - - MODE2 Clock Value 0x18 32 read-write n 0x0 0x0 DAY Day 17 5 HOUR Hour 12 5 HOURSelect AM AM when CLKREP in 12-hour 0 PM PM when CLKREP in 12-hour 16 MINUTE Minute 6 6 MONTH Month 22 4 SECOND Second 0 6 YEAR Year 26 6 MODE2 - CTRLA Clock/Calendar with Alarm - - MODE2 Control A 0x0 16 read-write n 0x0 0x0 BKTRST BKUP Registers Reset On Tamper Enable 13 1 CLKREP Clock Representation 6 1 CLOCKSYNC Clock Read Synchronization Enable 15 1 ENABLE Enable 1 1 GPTRST GP Registers Reset On Tamper Enable 14 1 MATCHCLR Clear on Match 7 1 MODE Operating Mode 2 2 MODESelect COUNT32 Mode 0: 32-bit Counter 0 COUNT16 Mode 1: 16-bit Counter 1 CLOCK Mode 2: Clock/Calendar 2 PRESCALER Prescaler 8 4 PRESCALERSelect OFF CLK_RTC_CNT = GCLK_RTC/1 0 DIV1 CLK_RTC_CNT = GCLK_RTC/1 1 DIV512 CLK_RTC_CNT = GCLK_RTC/512 10 DIV1024 CLK_RTC_CNT = GCLK_RTC/1024 11 DIV2 CLK_RTC_CNT = GCLK_RTC/2 2 DIV4 CLK_RTC_CNT = GCLK_RTC/4 3 DIV8 CLK_RTC_CNT = GCLK_RTC/8 4 DIV16 CLK_RTC_CNT = GCLK_RTC/16 5 DIV32 CLK_RTC_CNT = GCLK_RTC/32 6 DIV64 CLK_RTC_CNT = GCLK_RTC/64 7 DIV128 CLK_RTC_CNT = GCLK_RTC/128 8 DIV256 CLK_RTC_CNT = GCLK_RTC/256 9 SWRST Software Reset 0 1 MODE2 - CTRLB Clock/Calendar with Alarm - - MODE2 Control B 0x2 16 read-write n 0x0 0x0 ACTF Active Layer Freqnuency 12 3 ACTFSelect DIV2 CLK_RTC_OUT = CLK_RTC/2 0 DIV4 CLK_RTC_OUT = CLK_RTC/4 1 DIV8 CLK_RTC_OUT = CLK_RTC/8 2 DIV16 CLK_RTC_OUT = CLK_RTC/16 3 DIV32 CLK_RTC_OUT = CLK_RTC/32 4 DIV64 CLK_RTC_OUT = CLK_RTC/64 5 DIV128 CLK_RTC_OUT = CLK_RTC/128 6 DIV256 CLK_RTC_OUT = CLK_RTC/256 7 DEBASYNC Debouncer Asynchronous Enable 5 1 DEBF Debounce Freqnuency 8 3 DEBFSelect DIV2 CLK_RTC_DEB = CLK_RTC/2 0 DIV4 CLK_RTC_DEB = CLK_RTC/4 1 DIV8 CLK_RTC_DEB = CLK_RTC/8 2 DIV16 CLK_RTC_DEB = CLK_RTC/16 3 DIV32 CLK_RTC_DEB = CLK_RTC/32 4 DIV64 CLK_RTC_DEB = CLK_RTC/64 5 DIV128 CLK_RTC_DEB = CLK_RTC/128 6 DIV256 CLK_RTC_DEB = CLK_RTC/256 7 DEBMAJ Debouncer Majority Enable 4 1 DMAEN DMA Enable 7 1 GP0EN General Purpose 0 Enable 0 1 GP2EN General Purpose 2 Enable 1 1 RTCOUT RTC Output Enable 6 1 MODE2 - DBGCTRL Clock/Calendar with Alarm - - Debug Control 0xE 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 MODE2 - EVCTRL Clock/Calendar with Alarm - - MODE2 Event Control 0x4 32 read-write n 0x0 0x0 ALARMEO0 Alarm 0 Event Output Enable 8 1 ALARMEO1 Alarm 1 Event Output Enable 9 1 OVFEO Overflow Event Output Enable 15 1 PEREO0 Periodic Interval 0 Event Output Enable 0 1 PEREO1 Periodic Interval 1 Event Output Enable 1 1 PEREO2 Periodic Interval 2 Event Output Enable 2 1 PEREO3 Periodic Interval 3 Event Output Enable 3 1 PEREO4 Periodic Interval 4 Event Output Enable 4 1 PEREO5 Periodic Interval 5 Event Output Enable 5 1 PEREO6 Periodic Interval 6 Event Output Enable 6 1 PEREO7 Periodic Interval 7 Event Output Enable 7 1 TAMPEREO Tamper Event Output Enable 14 1 TAMPEVEI Tamper Event Input Enable 16 1 MODE2 - FREQCORR Clock/Calendar with Alarm - - Frequency Correction 0x14 8 read-write n 0x0 0x0 SIGN Correction Sign 7 1 VALUE Correction Value 0 7 MODE2 - GP[0] Clock/Calendar with Alarm - - General Purpose 0x80 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE2 - GP[1] Clock/Calendar with Alarm - - General Purpose 0xC4 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE2 - GP[2] Clock/Calendar with Alarm - - General Purpose 0x10C 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE2 - GP[3] Clock/Calendar with Alarm - - General Purpose 0x158 32 read-write n 0x0 0x0 GP General Purpose 0 32 MODE2 - INTENCLR Clock/Calendar with Alarm - - MODE2 Interrupt Enable Clear 0x8 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 ALARM1 Alarm 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Interrupt Enable 0 1 PER1 Periodic Interval 1 Interrupt Enable 1 1 PER2 Periodic Interval 2 Interrupt Enable 2 1 PER3 Periodic Interval 3 Interrupt Enable 3 1 PER4 Periodic Interval 4 Interrupt Enable 4 1 PER5 Periodic Interval 5 Interrupt Enable 5 1 PER6 Periodic Interval 6 Interrupt Enable 6 1 PER7 Periodic Interval 7 Interrupt Enable 7 1 TAMPER Tamper Enable 14 1 MODE2 - INTENSET Clock/Calendar with Alarm - - MODE2 Interrupt Enable Set 0xA 16 read-write n 0x0 0x0 ALARM0 Alarm 0 Interrupt Enable 8 1 ALARM1 Alarm 1 Interrupt Enable 9 1 OVF Overflow Interrupt Enable 15 1 PER0 Periodic Interval 0 Enable 0 1 PER1 Periodic Interval 1 Enable 1 1 PER2 Periodic Interval 2 Enable 2 1 PER3 Periodic Interval 3 Enable 3 1 PER4 Periodic Interval 4 Enable 4 1 PER5 Periodic Interval 5 Enable 5 1 PER6 Periodic Interval 6 Enable 6 1 PER7 Periodic Interval 7 Enable 7 1 TAMPER Tamper Enable 14 1 MODE2 - INTFLAG Clock/Calendar with Alarm - - MODE2 Interrupt Flag Status and Clear 0xC 16 read-write n 0x0 0x0 ALARM0 Alarm 0 8 1 ALARM1 Alarm 1 9 1 OVF Overflow 15 1 PER0 Periodic Interval 0 0 1 PER1 Periodic Interval 1 1 1 PER2 Periodic Interval 2 2 1 PER3 Periodic Interval 3 3 1 PER4 Periodic Interval 4 4 1 PER5 Periodic Interval 5 5 1 PER6 Periodic Interval 6 6 1 PER7 Periodic Interval 7 7 1 TAMPER Tamper 14 1 MODE2 - MASK0 Clock/Calendar with Alarm - - MODE2_ALARM Alarm n Mask 0x24 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0 SS Match seconds only 1 MMSS Match seconds and minutes only 2 HHMMSS Match seconds, minutes, and hours only 3 DDHHMMSS Match seconds, minutes, hours, and days only 4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 6 MODE2 - MASK1 Clock/Calendar with Alarm - - MODE2_ALARM Alarm n Mask 0x2C 8 read-write n 0x0 0x0 SEL Alarm Mask Selection 0 3 SELSelect OFF Alarm Disabled 0 SS Match seconds only 1 MMSS Match seconds and minutes only 2 HHMMSS Match seconds, minutes, and hours only 3 DDHHMMSS Match seconds, minutes, hours, and days only 4 MMDDHHMMSS Match seconds, minutes, hours, days, and months only 5 YYMMDDHHMMSS Match seconds, minutes, hours, days, months, and years 6 MODE2 - SYNCBUSY Clock/Calendar with Alarm - - MODE2 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 ALARM0 ALARM 0 Register Busy 5 1 ALARM1 ALARM 1 Register Busy 6 1 CLOCK CLOCK Register Busy 3 1 CLOCKSYNC Clock Synchronization Enable Bit Busy 15 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 MASK0 MASK 0 Register Busy 11 1 MASK1 MASK 1 Register Busy 12 1 SWRST Software Reset Bit Busy 0 1 MODE2 - TAMPCTRL Clock/Calendar with Alarm - - Tamper Control 0x60 32 read-write n 0x0 0x0 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN0 to OUT 3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN1 to OUT 3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN2 to OUT 3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN3 to OUT 3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0 WAKE Wake without timestamp 1 CAPTURE Capture timestamp 2 ACTL Compare IN4 to OUT 3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 MODE2 - TAMPID Clock/Calendar with Alarm - - Tamper ID 0x68 32 read-write n 0x0 0x0 TAMPEVT Tamper Event Detected 31 1 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 MODE2 - TIMESTAMP Clock/Calendar with Alarm - - MODE2 Timestamp 0x64 32 read-only n 0x0 0x0 DAY Day Timestamp Value 17 5 HOUR Hour Timestamp Value 12 5 HOURSelect AM AM when CLKREP in 12-hour 0 PM PM when CLKREP in 12-hour 16 MINUTE Minute Timestamp Value 6 6 MONTH Month Timestamp Value 22 4 SECOND Second Timestamp Value 0 6 YEAR Year Timestamp Value 26 6 PER MODE1 Counter Period 0x1C 16 read-write n 0x0 0x0 PER Counter Period 0 16 SYNCBUSY MODE2 Synchronization Busy Status 0x10 32 read-only n 0x0 0x0 ALARM0 ALARM 0 Register Busy 5 1 ALARM1 ALARM 1 Register Busy 6 1 CLOCK CLOCK Register Busy 3 1 CLOCKSYNC Clock Synchronization Enable Bit Busy 15 1 COMP0 COMP 0 Register Busy 5 1 COMP1 COMP 1 Register Busy 6 1 COMP2 COMP 2 Register Busy 7 1 COMP3 COMP 3 Register Busy 8 1 COUNT COUNT Register Busy 3 1 COUNTSYNC Count Synchronization Enable Bit Busy 15 1 ENABLE Enable Bit Busy 1 1 FREQCORR FREQCORR Register Busy 2 1 GP0 General Purpose 0 Register Busy 16 1 GP1 General Purpose 1 Register Busy 17 1 GP2 General Purpose 2 Register Busy 18 1 GP3 General Purpose 3 Register Busy 19 1 MASK0 MASK 0 Register Busy 11 1 MASK1 MASK 1 Register Busy 12 1 PER PER Register Busy 4 1 SWRST Software Reset Bit Busy 0 1 TAMPCTRL Tamper Control 0x60 32 read-write n 0x0 0x0 DEBNC0 Debouncer Enable 0 24 1 DEBNC1 Debouncer Enable 1 25 1 DEBNC2 Debouncer Enable 2 26 1 DEBNC3 Debouncer Enable 3 27 1 DEBNC4 Debouncer Enable 4 28 1 IN0ACT Tamper Input 0 Action 0 2 IN0ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN0 to OUT 0x3 IN1ACT Tamper Input 1 Action 2 2 IN1ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN1 to OUT 0x3 IN2ACT Tamper Input 2 Action 4 2 IN2ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN2 to OUT 0x3 IN3ACT Tamper Input 3 Action 6 2 IN3ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN3 to OUT 0x3 IN4ACT Tamper Input 4 Action 8 2 IN4ACTSelect OFF Off (Disabled) 0x0 WAKE Wake without timestamp 0x1 CAPTURE Capture timestamp 0x2 ACTL Compare IN4 to OUT 0x3 TAMLVL0 Tamper Level Select 0 16 1 TAMLVL1 Tamper Level Select 1 17 1 TAMLVL2 Tamper Level Select 2 18 1 TAMLVL3 Tamper Level Select 3 19 1 TAMLVL4 Tamper Level Select 4 20 1 TAMPID Tamper ID 0x68 32 read-write n 0x0 0x0 TAMPEVT Tamper Event Detected 31 1 TAMPID0 Tamper Input 0 Detected 0 1 TAMPID1 Tamper Input 1 Detected 1 1 TAMPID2 Tamper Input 2 Detected 2 1 TAMPID3 Tamper Input 3 Detected 3 1 TAMPID4 Tamper Input 4 Detected 4 1 TIMESTAMP MODE2 Timestamp 0x64 32 read-only n 0x0 0x0 COUNT Count Timestamp Value 0 16 DAY Day Timestamp Value 17 5 HOUR Hour Timestamp Value 12 5 HOURSelect AM AM when CLKREP in 12-hour 0x00 PM PM when CLKREP in 12-hour 0x10 MINUTE Minute Timestamp Value 6 6 MONTH Month Timestamp Value 22 4 SECOND Second Timestamp Value 0 6 YEAR Year Timestamp Value 26 6 SDHC0 SD/MMC Host Controller SDHC 0x0 0x0 0x235 registers n SDHC0 135 ACESR Auto CMD Error Status 0x3C 16 read-only n 0x0 0x0 ACMD12NE Auto CMD12 Not Executed 0 1 ACMD12NESelect EXEC Executed 0 NOT_EXEC Not executed 1 ACMDCRC Auto CMD CRC Error 2 1 ACMDCRCSelect NO No error 0 YES CRC Error Generated 1 ACMDEND Auto CMD End Bit Error 3 1 ACMDENDSelect NO No error 0 YES End Bit Error Generated 1 ACMDIDX Auto CMD Index Error 4 1 ACMDIDXSelect NO No error 0 YES Error 1 ACMDTEO Auto CMD Timeout Error 1 1 ACMDTEOSelect NO No error 0 YES Timeout 1 CMDNI Command not Issued By Auto CMD12 Error 7 1 CMDNISelect OK No error 0 NOT_ISSUED Not Issued 1 ACR AHB Control 0x208 32 read-write n 0x0 0x0 BMAX AHB Maximum Burst 0 2 BMAXSelect INCR16 0 INCR8 1 INCR4 2 SINGLE 3 AESR ADMA Error Status 0x54 8 read-only n 0x0 0x0 ERRST ADMA Error State 0 2 ERRSTSelect STOP ST_STOP (Stop DMA) 0 FDS ST_FDS (Fetch Descriptor) 1 TFR ST_TFR (Transfer Data) 3 LMIS ADMA Length Mismatch Error 2 1 LMISSelect NO No Error 0 YES Error 1 ARG1R Argument 1 0x8 32 read-write n 0x0 0x0 ARG Argument 1 0 32 ASAR1 ADMA System Address 0x58 32 read-write n 0x0 0x0 ADMASA ADMA System Address 0 32 BCR Block Count 0x6 16 read-write n 0x0 0x0 BCNT Blocks Count for Current Transfer 0 16 BDPR Buffer Data Port 0x20 32 read-write n 0x0 0x0 BUFDATA Buffer Data 0 32 BGCR Block Gap Control 0x2A 8 read-write n 0x0 0x0 CONTR Continue Request 1 1 CONTRSelect GO_ON Not affected 0 RESTART Restart 1 INTBG Interrupt at Block Gap 3 1 INTBGSelect DISABLED Disabled 0 ENABLED Enabled 1 RWCTRL Read Wait Control 2 1 RWCTRLSelect DISABLE Disable Read Wait Control 0 ENABLE Enable Read Wait Control 1 STPBGR Stop at Block Gap Request 0 1 STPBGRSelect TRANSFER Transfer 0 STOP Stop 1 BGCR_EMMC_MODE Block Gap Control BGCR 0x2A 8 read-write n 0x0 0x0 CONTR Continue Request 1 1 CONTRSelect GO_ON Not affected 0 RESTART Restart 1 STPBGR Stop at Block Gap Request 0 1 STPBGRSelect TRANSFER Transfer 0 STOP Stop 1 BSR Block Size 0x4 16 read-write n 0x0 0x0 BLOCKSIZE Transfer Block Size 0 10 BOUNDARY SDMA Buffer Boundary 12 3 BOUNDARYSelect 4K 4k bytes 0 8K 8k bytes 1 16K 16k bytes 2 32K 32k bytes 3 64K 64k bytes 4 128K 128k bytes 5 256K 256k bytes 6 512K 512k bytes 7 CA0R Capabilities 0 0x40 32 read-only n 0x0 0x0 ADMA2SUP ADMA2 Support 19 1 ADMA2SUPSelect NO ADMA2 not Supported 0 YES ADMA2 Supported 1 ASINTSUP Asynchronous Interrupt Support 29 1 ASINTSUPSelect NO Asynchronous Interrupt not Supported 0 YES Asynchronous Interrupt supported 1 BASECLKF Base Clock Frequency 8 8 BASECLKFSelect OTHER Get information via another method 0 ED8SUP 8-bit Support for Embedded Device 18 1 ED8SUPSelect NO 8-bit Bus Width not Supported 0 YES 8-bit Bus Width Supported 1 HSSUP High Speed Support 21 1 HSSUPSelect NO High Speed not Supported 0 YES High Speed Supported 1 MAXBLKL Max Block Length 16 2 MAXBLKLSelect 512 512 bytes 0 1024 1024 bytes 1 2048 2048 bytes 2 SB64SUP 64-Bit System Bus Support 28 1 SB64SUPSelect NO 32-bit Address Descriptors and System Bus 0 YES 64-bit Address Descriptors and System Bus 1 SDMASUP SDMA Support 22 1 SDMASUPSelect NO SDMA not Supported 0 YES SDMA Supported 1 SLTYPE Slot Type 30 2 SLTYPESelect REMOVABLE Removable Card Slot 0 EMBEDDED Embedded Slot for One Device 1 SRSUP Suspend/Resume Support 23 1 SRSUPSelect NO Suspend/Resume not Supported 0 YES Suspend/Resume Supported 1 TEOCLKF Timeout Clock Frequency 0 6 TEOCLKFSelect OTHER Get information via another method 0 TEOCLKU Timeout Clock Unit 7 1 TEOCLKUSelect KHZ KHz 0 MHZ MHz 1 V18VSUP Voltage Support 1.8V 26 1 V18VSUPSelect NO 1.8V Not Supported 0 YES 1.8V Supported 1 V30VSUP Voltage Support 3.0V 25 1 V30VSUPSelect NO 3.0V Not Supported 0 YES 3.0V Supported 1 V33VSUP Voltage Support 3.3V 24 1 V33VSUPSelect NO 3.3V Not Supported 0 YES 3.3V Supported 1 CA1R Capabilities 1 0x44 32 read-only n 0x0 0x0 CLKMULT Clock Multiplier 16 8 CLKMULTSelect NO Clock Multiplier is Not Supported 0 DDR50SUP DDR50 Support 2 1 DDR50SUPSelect NO DDR50 is Not Supported 0 YES DDR50 is Supported 1 DRVASUP Driver Type A Support 4 1 DRVASUPSelect NO Driver Type A is Not Supported 0 YES Driver Type A is Supported 1 DRVCSUP Driver Type C Support 5 1 DRVCSUPSelect NO Driver Type C is Not Supported 0 YES Driver Type C is Supported 1 DRVDSUP Driver Type D Support 6 1 DRVDSUPSelect NO Driver Type D is Not Supported 0 YES Driver Type D is Supported 1 SDR104SUP SDR104 Support 1 1 SDR104SUPSelect NO SDR104 is Not Supported 0 YES SDR104 is Supported 1 SDR50SUP SDR50 Support 0 1 SDR50SUPSelect NO SDR50 is Not Supported 0 YES SDR50 is Supported 1 TCNTRT Timer Count for Re-Tuning 8 4 TCNTRTSelect DISABLED Re-Tuning Timer disabled 0 1S 1 second 1 512S 512 seconds 10 1024S 1024 seconds 11 OTHER Get information from other source 15 2S 2 seconds 2 4S 4 seconds 3 8S 8 seconds 4 16S 16 seconds 5 32S 32 seconds 6 64S 64 seconds 7 128S 128 seconds 8 256S 256 seconds 9 TSDR50 Use Tuning for SDR50 13 1 TSDR50Select NO SDR50 does not require tuning 0 YES SDR50 requires tuning 1 CACR Capabilities Control 0x230 32 read-write n 0x0 0x0 CAPWREN Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) 0 1 KEY Key (0x46) 8 8 CC2R Clock Control 2 0x20C 32 read-write n 0x0 0x0 FSDCLKD Force SDCK Disabled 0 1 FSDCLKDSelect NOEFFECT No effect 0 DISABLE SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled 1 CCR Clock Control 0x2C 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select 5 1 CLKGSELSelect DIV Divided Clock Mode 0 PROG Programmable Clock Mode 1 INTCLKEN Internal Clock Enable 0 1 INTCLKENSelect OFF Stop 0 ON Oscillate 1 INTCLKS Internal Clock Stable 1 1 INTCLKSSelect NOT_READY Not Ready 0 READY Ready 1 SDCLKEN SD Clock Enable 2 1 SDCLKENSelect DISABLE Disable 0 ENABLE Enable 1 SDCLKFSEL SDCLK Frequency Select 8 8 USDCLKFSEL Upper Bits of SDCLK Frequency Select 6 2 CR Command 0xE 16 read-write n 0x0 0x0 CMDCCEN Command CRC Check Enable 3 1 CMDCCENSelect DISABLE Disable 0 ENABLE Enable 1 CMDICEN Command Index Check Enable 4 1 CMDICENSelect DISABLE Disable 0 ENABLE Enable 1 CMDIDX Command Index 8 6 CMDTYP Command Type 6 2 CMDTYPSelect NORMAL Other commands 0 SUSPEND CMD52 for writing Bus Suspend in CCCR 1 RESUME CMD52 for writing Function Select in CCCR 2 ABORT CMD12, CMD52 for writing I/O Abort in CCCR 3 DPSEL Data Present Select 5 1 DPSELSelect NO_DATA No Data Present 0 DATA Data Present 1 RESPTYP Response Type 0 2 RESPTYPSelect NONE No response 0 136_BIT 136-bit response 1 48_BIT 48-bit response 2 48_BIT_BUSY 48-bit response check busy after response 3 DBGR Debug 0x234 8 read-write n 0x0 0x0 NIDBG Non-intrusive debug enable 0 1 NIDBGSelect IDBG Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) 0 NIDBG Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) 1 EISIER Error Interrupt Signal Enable 0x3A 16 read-write n 0x0 0x0 ACMD Auto CMD Error Signal Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Signal Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Signal Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Signal Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Signal Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Signal Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Signal Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Signal Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Signal Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Signal Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 EISIER_EMMC_MODE Error Interrupt Signal Enable EISIER 0x3A 16 read-write n 0x0 0x0 ACMD Auto CMD Error Signal Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Signal Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 BOOTAE Boot Acknowledge Error Signal Enable 12 1 CMDCRC Command CRC Error Signal Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Signal Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Signal Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Signal Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Signal Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Signal Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Signal Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Signal Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 EISTER Error Interrupt Status Enable 0x36 16 read-write n 0x0 0x0 ACMD Auto CMD Error Status Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Status Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Status Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Status Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Status Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Status Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Status Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Status Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Status Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Status Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 EISTER_EMMC_MODE Error Interrupt Status Enable EISTER 0x36 16 read-write n 0x0 0x0 ACMD Auto CMD Error Status Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Status Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 BOOTAE Boot Acknowledge Error Status Enable 12 1 CMDCRC Command CRC Error Status Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Status Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Status Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Status Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Status Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Status Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Status Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Status Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 EISTR Error Interrupt Status 0x32 16 read-write n 0x0 0x0 ACMD Auto CMD Error 8 1 ACMDSelect NO No Error 0 YES Error 1 ADMA ADMA Error 9 1 ADMASelect NO No Error 0 YES Error 1 CMDCRC Command CRC Error 1 1 CMDCRCSelect NO No Error 0 YES CRC Error Generated 1 CMDEND Command End Bit Error 2 1 CMDENDSelect NO No error 0 YES End Bit Error Generated 1 CMDIDX Command Index Error 3 1 CMDIDXSelect NO No Error 0 YES Error 1 CMDTEO Command Timeout Error 0 1 CMDTEOSelect NO No Error 0 YES Timeout 1 CURLIM Current Limit Error 7 1 CURLIMSelect NO No Error 0 YES Power Fail 1 DATCRC Data CRC Error 5 1 DATCRCSelect NO No Error 0 YES Error 1 DATEND Data End Bit Error 6 1 DATENDSelect NO No Error 0 YES Error 1 DATTEO Data Timeout Error 4 1 DATTEOSelect NO No Error 0 YES Timeout 1 EISTR_EMMC_MODE Error Interrupt Status EISTR 0x32 16 read-write n 0x0 0x0 ACMD Auto CMD Error 8 1 ACMDSelect NO No Error 0 YES Error 1 ADMA ADMA Error 9 1 ADMASelect NO No Error 0 YES Error 1 BOOTAE Boot Acknowledge Error 12 1 BOOTAESelect 0 FIFO contains at least one byte 0 1 FIFO is empty 1 CMDCRC Command CRC Error 1 1 CMDCRCSelect NO No Error 0 YES CRC Error Generated 1 CMDEND Command End Bit Error 2 1 CMDENDSelect NO No error 0 YES End Bit Error Generated 1 CMDIDX Command Index Error 3 1 CMDIDXSelect NO No Error 0 YES Error 1 CMDTEO Command Timeout Error 0 1 CMDTEOSelect NO No Error 0 YES Timeout 1 CURLIM Current Limit Error 7 1 CURLIMSelect NO No Error 0 YES Power Fail 1 DATCRC Data CRC Error 5 1 DATCRCSelect NO No Error 0 YES Error 1 DATEND Data End Bit Error 6 1 DATENDSelect NO No Error 0 YES Error 1 DATTEO Data Timeout Error 4 1 DATTEOSelect NO No Error 0 YES Timeout 1 FERACES Force Event for Auto CMD Error Status 0x50 16 write-only n 0x0 0x0 ACMD12NE Force Event for Auto CMD12 Not Executed 0 1 ACMD12NESelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDCRC Force Event for Auto CMD CRC Error 2 1 ACMDCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDEND Force Event for Auto CMD End Bit Error 3 1 ACMDENDSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDIDX Force Event for Auto CMD Index Error 4 1 ACMDIDXSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDTEO Force Event for Auto CMD Timeout Error 1 1 ACMDTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDNI Force Event for Command Not Issued By Auto CMD12 Error 7 1 CMDNISelect NO No Interrupt 0 YES Interrupt is generated 1 FEREIS Force Event for Error Interrupt Status 0x52 16 write-only n 0x0 0x0 ACMD Force Event for Auto CMD Error 8 1 ACMDSelect NO No Interrupt 0 YES Interrupt is generated 1 ADMA Force Event for ADMA Error 9 1 ADMASelect NO No Interrupt 0 YES Interrupt is generated 1 BOOTAE Force Event for Boot Acknowledge Error 12 1 BOOTAESelect NO No Interrupt 0 YES Interrupt is generated 1 CMDCRC Force Event for Command CRC Error 1 1 CMDCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDEND Force Event for Command End Bit Error 2 1 CMDENDSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDIDX Force Event for Command Index Error 3 1 CMDIDXSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDTEO Force Event for Command Timeout Error 0 1 CMDTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 CURLIM Force Event for Current Limit Error 7 1 CURLIMSelect NO No Interrupt 0 YES Interrupt is generated 1 DATCRC Force Event for Data CRC Error 5 1 DATCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 DATEND Force Event for Data End Bit Error 6 1 DATENDSelect NO No Interrupt 0 YES Interrupt is generated 1 DATTEO Force Event for Data Timeout Error 4 1 DATTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 HC1R Host Control 1 0x28 8 read-write n 0x0 0x0 CARDDSEL Card Detect Signal Selection 7 1 CARDDSELSelect NORMAL SDCD# is selected (for normal use) 0 TEST The Card Select Test Level is selected (for test purpose) 1 CARDDTL Card Detect Test Level 6 1 CARDDTLSelect NO No Card 0 YES Card Inserted 1 DMASEL DMA Select 3 2 DMASELSelect SDMA SDMA is selected 0 32BIT 32-bit Address ADMA2 is selected 2 DW Data Width 1 1 DWSelect 1BIT 1-bit mode 0 4BIT 4-bit mode 1 HSEN High Speed Enable 2 1 HSENSelect NORMAL Normal Speed mode 0 HIGH High Speed mode 1 LEDCTRL LED Control 0 1 LEDCTRLSelect OFF LED off 0 ON LED on 1 HC1R_EMMC_MODE Host Control 1 HC1R 0x28 8 read-write n 0x0 0x0 DMASEL DMA Select 3 2 DMASELSelect SDMA SDMA is selected 0 32BIT 32-bit Address ADMA2 is selected 2 DW Data Width 1 1 DWSelect 1BIT 1-bit mode 0 4BIT 4-bit mode 1 HSEN High Speed Enable 2 1 HSENSelect NORMAL Normal Speed mode 0 HIGH High Speed mode 1 HC2R Host Control 2 0x3E 16 read-write n 0x0 0x0 ASINTEN Asynchronous Interrupt Enable 14 1 ASINTENSelect DISABLED Disabled 0 ENABLED Enabled 1 DRVSEL Driver Strength Select 4 2 DRVSELSelect B Driver Type B is Selected (Default) 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 EXTUN Execute Tuning 6 1 EXTUNSelect NO Not Tuned or Tuning Completed 0 REQUESTED Execute Tuning 1 PVALEN Preset Value Enable 15 1 PVALENSelect HOST SDCLK and Driver Strength are controlled by Host Controller 0 AUTO Automatic Selection by Preset Value is Enabled 1 SLCKSEL Sampling Clock Select 7 1 SLCKSELSelect FIXED Fixed clock is used to sample data 0 TUNED Tuned clock is used to sample data 1 UHSMS UHS Mode Select 0 3 UHSMSSelect SDR12 SDR12 0 SDR25 SDR25 1 SDR50 SDR50 2 SDR104 SDR104 3 DDR50 DDR50 4 VS18EN 1.8V Signaling Enable 3 1 VS18ENSelect S33V 3.3V Signaling 0 S18V 1.8V Signaling 1 HC2R_EMMC_MODE Host Control 2 HC2R 0x3E 16 read-write n 0x0 0x0 DRVSEL Driver Strength Select 4 2 DRVSELSelect B Driver Type B is Selected (Default) 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 EXTUN Execute Tuning 6 1 EXTUNSelect NO Not Tuned or Tuning Completed 0 REQUESTED Execute Tuning 1 HS200EN HS200 Mode Enable 0 4 HS200ENSelect SDR12 SDR12 0 SDR25 SDR25 1 SDR50 SDR50 2 SDR104 SDR104 3 DDR50 DDR50 4 PVALEN Preset Value Enable 15 1 PVALENSelect HOST SDCLK and Driver Strength are controlled by Host Controller 0 AUTO Automatic Selection by Preset Value is Enabled 1 SLCKSEL Sampling Clock Select 7 1 SLCKSELSelect FIXED Fixed clock is used to sample data 0 TUNED Tuned clock is used to sample data 1 HCVR Host Controller Version 0xFE 16 read-only n 0x0 0x0 SVER Spec Version 0 8 VVER Vendor Version 8 8 MC1R MMC Control 1 0x204 8 read-write n 0x0 0x0 BOOTA e.MMC Boot Acknowledge Enable 5 1 CMDTYP e.MMC Command Type 0 2 CMDTYPSelect NORMAL Not a MMC specific command 0 WAITIRQ Wait IRQ Command 1 STREAM Stream Command 2 BOOT Boot Command 3 DDR e.MMC HSDDR Mode 3 1 FCD e.MMC Force Card Detect 7 1 OPD e.MMC Open Drain Mode 4 1 RSTN e.MMC Reset Signal 6 1 MC2R MMC Control 2 0x205 8 write-only n 0x0 0x0 ABOOT e.MMC Abort Boot 1 1 SRESP e.MMC Abort Wait IRQ 0 1 MCCAR Maximum Current Capabilities 0x48 32 read-only n 0x0 0x0 MAXCUR18V Maximum Current for 1.8V 16 8 MAXCUR18VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 MAXCUR30V Maximum Current for 3.0V 8 8 MAXCUR30VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 MAXCUR33V Maximum Current for 3.3V 0 8 MAXCUR33VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 NISIER Normal Interrupt Signal Enable 0x38 16 read-write n 0x0 0x0 BLKGE Block Gap Event Signal Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Signal Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Signal Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CINS Card Insertion Signal Enable 6 1 CINSSelect MASKED Masked 0 ENABLED Enabled 1 CINT Card Interrupt Signal Enable 8 1 CINTSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Signal Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 CREM Card Removal Signal Enable 7 1 CREMSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Signal Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Signal Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 NISIER_EMMC_MODE Normal Interrupt Signal Enable NISIER 0x38 16 read-write n 0x0 0x0 BLKGE Block Gap Event Signal Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BOOTAR Boot Acknowledge Received Signal Enable 14 1 BRDRDY Buffer Read Ready Signal Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Signal Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Signal Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Signal Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Signal Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 NISTER Normal Interrupt Status Enable 0x34 16 read-write n 0x0 0x0 BLKGE Block Gap Event Status Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Status Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Status Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CINS Card Insertion Status Enable 6 1 CINSSelect MASKED Masked 0 ENABLED Enabled 1 CINT Card Interrupt Status Enable 8 1 CINTSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Status Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 CREM Card Removal Status Enable 7 1 CREMSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Status Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Status Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 NISTER_EMMC_MODE Normal Interrupt Status Enable NISTER 0x34 16 read-write n 0x0 0x0 BLKGE Block Gap Event Status Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BOOTAR Boot Acknowledge Received Status Enable 14 1 BRDRDY Buffer Read Ready Status Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Status Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Status Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Status Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Status Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 NISTR Normal Interrupt Status 0x30 16 read-write n 0x0 0x0 BLKGE Block Gap Event 2 1 BLKGESelect NO No Block Gap Event 0 STOP Transaction stopped at block gap 1 BRDRDY Buffer Read Ready 5 1 BRDRDYSelect NO Not ready to read buffer 0 YES Ready to read buffer 1 BWRRDY Buffer Write Ready 4 1 BWRRDYSelect NO Not ready to write buffer 0 YES Ready to write buffer 1 CINS Card Insertion 6 1 CINSSelect NO Card state stable or Debouncing 0 YES Card inserted 1 CINT Card Interrupt 8 1 CINTSelect NO No Card Interrupt 0 YES Generate Card Interrupt 1 CMDC Command Complete 0 1 CMDCSelect NO No command complete 0 YES Command complete 1 CREM Card Removal 7 1 CREMSelect NO Card state stable or Debouncing 0 YES Card Removed 1 DMAINT DMA Interrupt 3 1 DMAINTSelect NO No DMA Interrupt 0 YES DMA Interrupt is generated 1 ERRINT Error Interrupt 15 1 ERRINTSelect NO No Error 0 YES Error 1 TRFC Transfer Complete 1 1 TRFCSelect NO Not complete 0 YES Command execution is completed 1 NISTR_EMMC_MODE Normal Interrupt Status NISTR 0x30 16 read-write n 0x0 0x0 BLKGE Block Gap Event 2 1 BLKGESelect NO No Block Gap Event 0 STOP Transaction stopped at block gap 1 BOOTAR Boot Acknowledge Received 14 1 BRDRDY Buffer Read Ready 5 1 BRDRDYSelect NO Not ready to read buffer 0 YES Ready to read buffer 1 BWRRDY Buffer Write Ready 4 1 BWRRDYSelect NO Not ready to write buffer 0 YES Ready to write buffer 1 CMDC Command Complete 0 1 CMDCSelect NO No command complete 0 YES Command complete 1 DMAINT DMA Interrupt 3 1 DMAINTSelect NO No DMA Interrupt 0 YES DMA Interrupt is generated 1 ERRINT Error Interrupt 15 1 ERRINTSelect NO No Error 0 YES Error 1 TRFC Transfer Complete 1 1 TRFCSelect NO Not complete 0 YES Command execution is completed 1 PCR Power Control 0x29 8 read-write n 0x0 0x0 SDBPWR SD Bus Power 0 1 SDBPWRSelect OFF Power off 0 ON Power on 1 SDBVSEL SD Bus Voltage Select 1 3 SDBVSELSelect 1V8 1.8V (Typ.) 5 3V0 3.0V (Typ.) 6 3V3 3.3V (Typ.) 7 PSR Present State 0x24 32 read-only n 0x0 0x0 BUFRDEN Buffer Read Enable 11 1 BUFRDENSelect DISABLE Read disable 0 ENABLE Read enable 1 BUFWREN Buffer Write Enable 10 1 BUFWRENSelect DISABLE Write disable 0 ENABLE Write enable 1 CARDDPL Card Detect Pin Level 18 1 CARDDPLSelect NO No card present (SDCD#=1) 0 YES Card present (SDCD#=0) 1 CARDINS Card Inserted 16 1 CARDINSSelect NO Reset or Debouncing or No Card 0 YES Card inserted 1 CARDSS Card State Stable 17 1 CARDSSSelect NO Reset or Debouncing 0 YES No Card or Insered 1 CMDINHC Command Inhibit (CMD) 0 1 CMDINHCSelect CAN Can issue command using only CMD line 0 CANNOT Cannot issue command 1 CMDINHD Command Inhibit (DAT) 1 1 CMDINHDSelect CAN Can issue command which uses the DAT line 0 CANNOT Cannot issue command which uses the DAT line 1 CMDLL CMD Line Level 24 1 DATLL DAT[3:0] Line Level 20 4 DLACT DAT Line Active 2 1 DLACTSelect INACTIVE DAT Line Inactive 0 ACTIVE DAT Line Active 1 RTACT Read Transfer Active 9 1 RTACTSelect NO No valid data 0 YES Transferring data 1 RTREQ Re-Tuning Request 3 1 RTREQSelect OK Fixed or well-tuned sampling clock 0 REQUIRED Sampling clock needs re-tuning 1 WRPPL Write Protect Pin Level 19 1 WRPPLSelect PROTECTED Write protected (SDWP#=0) 0 ENABLED Write enabled (SDWP#=1) 1 WTACT Write Transfer Active 8 1 WTACTSelect NO No valid data 0 YES Transferring data 1 PVR0 Preset Value n 0x60 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR1 Preset Value n 0x62 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR2 Preset Value n 0x64 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR3 Preset Value n 0x66 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR4 Preset Value n 0x68 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR5 Preset Value n 0x6A 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR6 Preset Value n 0x6C 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 PVR7 Preset Value n 0x6E 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 RR0 Response 0x10 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 RR1 Response 0x14 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 RR2 Response 0x18 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 RR3 Response 0x1C 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 SDHC_ACESR Auto CMD Error Status 0x3C 16 read-only n 0x0 0x0 ACMD12NE Auto CMD12 Not Executed 0 1 ACMD12NESelect EXEC Executed 0 NOT_EXEC Not executed 1 ACMDCRC Auto CMD CRC Error 2 1 ACMDCRCSelect NO No error 0 YES CRC Error Generated 1 ACMDEND Auto CMD End Bit Error 3 1 ACMDENDSelect NO No error 0 YES End Bit Error Generated 1 ACMDIDX Auto CMD Index Error 4 1 ACMDIDXSelect NO No error 0 YES Error 1 ACMDTEO Auto CMD Timeout Error 1 1 ACMDTEOSelect NO No error 0 YES Timeout 1 CMDNI Command not Issued By Auto CMD12 Error 7 1 CMDNISelect OK No error 0 NOT_ISSUED Not Issued 1 SDHC_ACR AHB Control 0x208 32 read-write n 0x0 0x0 BMAX AHB Maximum Burst 0 2 BMAXSelect INCR16 None 0 INCR8 None 1 INCR4 None 2 SINGLE None 3 SDHC_AESR ADMA Error Status 0x54 8 read-only n 0x0 0x0 ERRST ADMA Error State 0 2 ERRSTSelect STOP ST_STOP (Stop DMA) 0 FDS ST_FDS (Fetch Descriptor) 1 TFR ST_TFR (Transfer Data) 3 LMIS ADMA Length Mismatch Error 2 1 LMISSelect NO No Error 0 YES Error 1 SDHC_ARG1R Argument 1 0x8 32 read-write n 0x0 0x0 ARG Argument 1 0 32 SDHC_ASAR[0] ADMA System Address n 0xB0 32 read-write n 0x0 0x0 ADMASA ADMA System Address 0 32 SDHC_BCR Block Count 0x6 16 read-write n 0x0 0x0 BCNT Blocks Count for Current Transfer 0 16 SDHC_BDPR Buffer Data Port 0x20 32 read-write n 0x0 0x0 BUFDATA Buffer Data 0 32 SDHC_BGCR Block Gap Control 0x2A 8 read-write n 0x0 0x0 CONTR Continue Request 1 1 CONTRSelect GO_ON Not affected 0 RESTART Restart 1 INTBG Interrupt at Block Gap 3 1 INTBGSelect DISABLED Disabled 0 ENABLED Enabled 1 RWCTRL Read Wait Control 2 1 RWCTRLSelect DISABLE Disable Read Wait Control 0 ENABLE Enable Read Wait Control 1 STPBGR Stop at Block Gap Request 0 1 STPBGRSelect TRANSFER Transfer 0 STOP Stop 1 SDHC_BGCR_EMMC_MODE Block Gap Control BGCR 0x2A 8 read-write n 0x0 0x0 CONTR Continue Request 1 1 CONTRSelect GO_ON Not affected 0 RESTART Restart 1 STPBGR Stop at Block Gap Request 0 1 STPBGRSelect TRANSFER Transfer 0 STOP Stop 1 SDHC_BSR Block Size 0x4 16 read-write n 0x0 0x0 BLOCKSIZE Transfer Block Size 0 10 BOUNDARY SDMA Buffer Boundary 12 3 BOUNDARYSelect 4K 4k bytes 0 8K 8k bytes 1 16K 16k bytes 2 32K 32k bytes 3 64K 64k bytes 4 128K 128k bytes 5 256K 256k bytes 6 512K 512k bytes 7 SDHC_CA0R Capabilities 0 0x40 32 read-only n 0x0 0x0 ADMA2SUP ADMA2 Support 19 1 ADMA2SUPSelect NO ADMA2 not Supported 0 YES ADMA2 Supported 1 ASINTSUP Asynchronous Interrupt Support 29 1 ASINTSUPSelect NO Asynchronous Interrupt not Supported 0 YES Asynchronous Interrupt supported 1 BASECLKF Base Clock Frequency 8 8 BASECLKFSelect OTHER Get information via another method 0 ED8SUP 8-bit Support for Embedded Device 18 1 ED8SUPSelect NO 8-bit Bus Width not Supported 0 YES 8-bit Bus Width Supported 1 HSSUP High Speed Support 21 1 HSSUPSelect NO High Speed not Supported 0 YES High Speed Supported 1 MAXBLKL Max Block Length 16 2 MAXBLKLSelect 512 512 bytes 0 1024 1024 bytes 1 2048 2048 bytes 2 SB64SUP 64-Bit System Bus Support 28 1 SB64SUPSelect NO 32-bit Address Descriptors and System Bus 0 YES 64-bit Address Descriptors and System Bus 1 SDMASUP SDMA Support 22 1 SDMASUPSelect NO SDMA not Supported 0 YES SDMA Supported 1 SLTYPE Slot Type 30 2 SLTYPESelect REMOVABLE Removable Card Slot 0 EMBEDDED Embedded Slot for One Device 1 SRSUP Suspend/Resume Support 23 1 SRSUPSelect NO Suspend/Resume not Supported 0 YES Suspend/Resume Supported 1 TEOCLKF Timeout Clock Frequency 0 6 TEOCLKFSelect OTHER Get information via another method 0 TEOCLKU Timeout Clock Unit 7 1 TEOCLKUSelect KHZ KHz 0 MHZ MHz 1 V18VSUP Voltage Support 1.8V 26 1 V18VSUPSelect NO 1.8V Not Supported 0 YES 1.8V Supported 1 V30VSUP Voltage Support 3.0V 25 1 V30VSUPSelect NO 3.0V Not Supported 0 YES 3.0V Supported 1 V33VSUP Voltage Support 3.3V 24 1 V33VSUPSelect NO 3.3V Not Supported 0 YES 3.3V Supported 1 SDHC_CA1R Capabilities 1 0x44 32 read-only n 0x0 0x0 CLKMULT Clock Multiplier 16 8 CLKMULTSelect NO Clock Multiplier is Not Supported 0 DDR50SUP DDR50 Support 2 1 DDR50SUPSelect NO DDR50 is Not Supported 0 YES DDR50 is Supported 1 DRVASUP Driver Type A Support 4 1 DRVASUPSelect NO Driver Type A is Not Supported 0 YES Driver Type A is Supported 1 DRVCSUP Driver Type C Support 5 1 DRVCSUPSelect NO Driver Type C is Not Supported 0 YES Driver Type C is Supported 1 DRVDSUP Driver Type D Support 6 1 DRVDSUPSelect NO Driver Type D is Not Supported 0 YES Driver Type D is Supported 1 SDR104SUP SDR104 Support 1 1 SDR104SUPSelect NO SDR104 is Not Supported 0 YES SDR104 is Supported 1 SDR50SUP SDR50 Support 0 1 SDR50SUPSelect NO SDR50 is Not Supported 0 YES SDR50 is Supported 1 TCNTRT Timer Count for Re-Tuning 8 4 TCNTRTSelect DISABLED Re-Tuning Timer disabled 0 1S 1 second 1 512S 512 seconds 10 1024S 1024 seconds 11 OTHER Get information from other source 15 2S 2 seconds 2 4S 4 seconds 3 8S 8 seconds 4 16S 16 seconds 5 32S 32 seconds 6 64S 64 seconds 7 128S 128 seconds 8 256S 256 seconds 9 TSDR50 Use Tuning for SDR50 13 1 TSDR50Select NO SDR50 does not require tuning 0 YES SDR50 requires tuning 1 SDHC_CACR Capabilities Control 0x230 32 read-write n 0x0 0x0 CAPWREN Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) 0 1 KEY Key (0x46) 8 8 SDHC_CC2R Clock Control 2 0x20C 32 read-write n 0x0 0x0 FSDCLKD Force SDCK Disabled 0 1 FSDCLKDSelect NOEFFECT No effect 0 DISABLE SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled 1 SDHC_CCR Clock Control 0x2C 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select 5 1 CLKGSELSelect DIV Divided Clock Mode 0 PROG Programmable Clock Mode 1 INTCLKEN Internal Clock Enable 0 1 INTCLKENSelect OFF Stop 0 ON Oscillate 1 INTCLKS Internal Clock Stable 1 1 INTCLKSSelect NOT_READY Not Ready 0 READY Ready 1 SDCLKEN SD Clock Enable 2 1 SDCLKENSelect DISABLE Disable 0 ENABLE Enable 1 SDCLKFSEL SDCLK Frequency Select 8 8 USDCLKFSEL Upper Bits of SDCLK Frequency Select 6 2 SDHC_CR Command 0xE 16 read-write n 0x0 0x0 CMDCCEN Command CRC Check Enable 3 1 CMDCCENSelect DISABLE Disable 0 ENABLE Enable 1 CMDICEN Command Index Check Enable 4 1 CMDICENSelect DISABLE Disable 0 ENABLE Enable 1 CMDIDX Command Index 8 6 CMDTYP Command Type 6 2 CMDTYPSelect NORMAL Other commands 0 SUSPEND CMD52 for writing Bus Suspend in CCCR 1 RESUME CMD52 for writing Function Select in CCCR 2 ABORT CMD12, CMD52 for writing I/O Abort in CCCR 3 DPSEL Data Present Select 5 1 DPSELSelect NO_DATA No Data Present 0 DATA Data Present 1 RESPTYP Response Type 0 2 RESPTYPSelect NONE No response 0 136_BIT 136-bit response 1 48_BIT 48-bit response 2 48_BIT_BUSY 48-bit response check busy after response 3 SDHC_DBGR Debug 0x234 8 read-write n 0x0 0x0 NIDBG Non-intrusive debug enable 0 1 NIDBGSelect IDBG Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) 0 NIDBG Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) 1 SDHC_EISIER Error Interrupt Signal Enable 0x3A 16 read-write n 0x0 0x0 ACMD Auto CMD Error Signal Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Signal Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Signal Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Signal Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Signal Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Signal Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Signal Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Signal Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Signal Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Signal Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_EISIER_EMMC_MODE Error Interrupt Signal Enable EISIER 0x3A 16 read-write n 0x0 0x0 ACMD Auto CMD Error Signal Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Signal Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 BOOTAE Boot Acknowledge Error Signal Enable 12 1 CMDCRC Command CRC Error Signal Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Signal Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Signal Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Signal Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Signal Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Signal Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Signal Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Signal Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_EISTER Error Interrupt Status Enable 0x36 16 read-write n 0x0 0x0 ACMD Auto CMD Error Status Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Status Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 CMDCRC Command CRC Error Status Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Status Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Status Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Status Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Status Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Status Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Status Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Status Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_EISTER_EMMC_MODE Error Interrupt Status Enable EISTER 0x36 16 read-write n 0x0 0x0 ACMD Auto CMD Error Status Enable 8 1 ACMDSelect MASKED Masked 0 ENABLED Enabled 1 ADMA ADMA Error Status Enable 9 1 ADMASelect MASKED Masked 0 ENABLED Enabled 1 BOOTAE Boot Acknowledge Error Status Enable 12 1 CMDCRC Command CRC Error Status Enable 1 1 CMDCRCSelect MASKED Masked 0 ENABLED Enabled 1 CMDEND Command End Bit Error Status Enable 2 1 CMDENDSelect MASKED Masked 0 ENABLED Enabled 1 CMDIDX Command Index Error Status Enable 3 1 CMDIDXSelect MASKED Masked 0 ENABLED Enabled 1 CMDTEO Command Timeout Error Status Enable 0 1 CMDTEOSelect MASKED Masked 0 ENABLED Enabled 1 CURLIM Current Limit Error Status Enable 7 1 CURLIMSelect MASKED Masked 0 ENABLED Enabled 1 DATCRC Data CRC Error Status Enable 5 1 DATCRCSelect MASKED Masked 0 ENABLED Enabled 1 DATEND Data End Bit Error Status Enable 6 1 DATENDSelect MASKED Masked 0 ENABLED Enabled 1 DATTEO Data Timeout Error Status Enable 4 1 DATTEOSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_EISTR Error Interrupt Status 0x32 16 read-write n 0x0 0x0 ACMD Auto CMD Error 8 1 ACMDSelect NO No Error 0 YES Error 1 ADMA ADMA Error 9 1 ADMASelect NO No Error 0 YES Error 1 CMDCRC Command CRC Error 1 1 CMDCRCSelect NO No Error 0 YES CRC Error Generated 1 CMDEND Command End Bit Error 2 1 CMDENDSelect NO No error 0 YES End Bit Error Generated 1 CMDIDX Command Index Error 3 1 CMDIDXSelect NO No Error 0 YES Error 1 CMDTEO Command Timeout Error 0 1 CMDTEOSelect NO No Error 0 YES Timeout 1 CURLIM Current Limit Error 7 1 CURLIMSelect NO No Error 0 YES Power Fail 1 DATCRC Data CRC Error 5 1 DATCRCSelect NO No Error 0 YES Error 1 DATEND Data End Bit Error 6 1 DATENDSelect NO No Error 0 YES Error 1 DATTEO Data Timeout Error 4 1 DATTEOSelect NO No Error 0 YES Timeout 1 SDHC_EISTR_EMMC_MODE Error Interrupt Status EISTR 0x32 16 read-write n 0x0 0x0 ACMD Auto CMD Error 8 1 ACMDSelect NO No Error 0 YES Error 1 ADMA ADMA Error 9 1 ADMASelect NO No Error 0 YES Error 1 BOOTAE Boot Acknowledge Error 12 1 BOOTAESelect 0 FIFO contains at least one byte 0 1 FIFO is empty 1 CMDCRC Command CRC Error 1 1 CMDCRCSelect NO No Error 0 YES CRC Error Generated 1 CMDEND Command End Bit Error 2 1 CMDENDSelect NO No error 0 YES End Bit Error Generated 1 CMDIDX Command Index Error 3 1 CMDIDXSelect NO No Error 0 YES Error 1 CMDTEO Command Timeout Error 0 1 CMDTEOSelect NO No Error 0 YES Timeout 1 CURLIM Current Limit Error 7 1 CURLIMSelect NO No Error 0 YES Power Fail 1 DATCRC Data CRC Error 5 1 DATCRCSelect NO No Error 0 YES Error 1 DATEND Data End Bit Error 6 1 DATENDSelect NO No Error 0 YES Error 1 DATTEO Data Timeout Error 4 1 DATTEOSelect NO No Error 0 YES Timeout 1 SDHC_FERACES Force Event for Auto CMD Error Status 0x50 16 write-only n 0x0 0x0 ACMD12NE Force Event for Auto CMD12 Not Executed 0 1 ACMD12NESelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDCRC Force Event for Auto CMD CRC Error 2 1 ACMDCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDEND Force Event for Auto CMD End Bit Error 3 1 ACMDENDSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDIDX Force Event for Auto CMD Index Error 4 1 ACMDIDXSelect NO No Interrupt 0 YES Interrupt is generated 1 ACMDTEO Force Event for Auto CMD Timeout Error 1 1 ACMDTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDNI Force Event for Command Not Issued By Auto CMD12 Error 7 1 CMDNISelect NO No Interrupt 0 YES Interrupt is generated 1 SDHC_FEREIS Force Event for Error Interrupt Status 0x52 16 write-only n 0x0 0x0 ACMD Force Event for Auto CMD Error 8 1 ACMDSelect NO No Interrupt 0 YES Interrupt is generated 1 ADMA Force Event for ADMA Error 9 1 ADMASelect NO No Interrupt 0 YES Interrupt is generated 1 BOOTAE Force Event for Boot Acknowledge Error 12 1 BOOTAESelect NO No Interrupt 0 YES Interrupt is generated 1 CMDCRC Force Event for Command CRC Error 1 1 CMDCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDEND Force Event for Command End Bit Error 2 1 CMDENDSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDIDX Force Event for Command Index Error 3 1 CMDIDXSelect NO No Interrupt 0 YES Interrupt is generated 1 CMDTEO Force Event for Command Timeout Error 0 1 CMDTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 CURLIM Force Event for Current Limit Error 7 1 CURLIMSelect NO No Interrupt 0 YES Interrupt is generated 1 DATCRC Force Event for Data CRC Error 5 1 DATCRCSelect NO No Interrupt 0 YES Interrupt is generated 1 DATEND Force Event for Data End Bit Error 6 1 DATENDSelect NO No Interrupt 0 YES Interrupt is generated 1 DATTEO Force Event for Data Timeout Error 4 1 DATTEOSelect NO No Interrupt 0 YES Interrupt is generated 1 SDHC_HC1R Host Control 1 0x28 8 read-write n 0x0 0x0 CARDDSEL Card Detect Signal Selection 7 1 CARDDSELSelect NORMAL SDCD# is selected (for normal use) 0 TEST The Card Select Test Level is selected (for test purpose) 1 CARDDTL Card Detect Test Level 6 1 CARDDTLSelect NO No Card 0 YES Card Inserted 1 DMASEL DMA Select 3 2 DMASELSelect SDMA SDMA is selected 0 32BIT 32-bit Address ADMA2 is selected 2 DW Data Width 1 1 DWSelect 1BIT 1-bit mode 0 4BIT 4-bit mode 1 HSEN High Speed Enable 2 1 HSENSelect NORMAL Normal Speed mode 0 HIGH High Speed mode 1 LEDCTRL LED Control 0 1 LEDCTRLSelect OFF LED off 0 ON LED on 1 SDHC_HC1R_EMMC_MODE Host Control 1 HC1R 0x28 8 read-write n 0x0 0x0 DMASEL DMA Select 3 2 DMASELSelect SDMA SDMA is selected 0 32BIT 32-bit Address ADMA2 is selected 2 DW Data Width 1 1 DWSelect 1BIT 1-bit mode 0 4BIT 4-bit mode 1 HSEN High Speed Enable 2 1 HSENSelect NORMAL Normal Speed mode 0 HIGH High Speed mode 1 SDHC_HC2R Host Control 2 0x3E 16 read-write n 0x0 0x0 ASINTEN Asynchronous Interrupt Enable 14 1 ASINTENSelect DISABLED Disabled 0 ENABLED Enabled 1 DRVSEL Driver Strength Select 4 2 DRVSELSelect B Driver Type B is Selected (Default) 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 EXTUN Execute Tuning 6 1 EXTUNSelect NO Not Tuned or Tuning Completed 0 REQUESTED Execute Tuning 1 PVALEN Preset Value Enable 15 1 PVALENSelect HOST SDCLK and Driver Strength are controlled by Host Controller 0 AUTO Automatic Selection by Preset Value is Enabled 1 SLCKSEL Sampling Clock Select 7 1 SLCKSELSelect FIXED Fixed clock is used to sample data 0 TUNED Tuned clock is used to sample data 1 UHSMS UHS Mode Select 0 3 UHSMSSelect SDR12 SDR12 0 SDR25 SDR25 1 SDR50 SDR50 2 SDR104 SDR104 3 DDR50 DDR50 4 VS18EN 1.8V Signaling Enable 3 1 VS18ENSelect S33V 3.3V Signaling 0 S18V 1.8V Signaling 1 SDHC_HC2R_EMMC_MODE Host Control 2 HC2R 0x3E 16 read-write n 0x0 0x0 DRVSEL Driver Strength Select 4 2 DRVSELSelect B Driver Type B is Selected (Default) 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 EXTUN Execute Tuning 6 1 EXTUNSelect NO Not Tuned or Tuning Completed 0 REQUESTED Execute Tuning 1 HS200EN HS200 Mode Enable 0 4 HS200ENSelect SDR12 SDR12 0 SDR25 SDR25 1 SDR50 SDR50 2 SDR104 SDR104 3 DDR50 DDR50 4 PVALEN Preset Value Enable 15 1 PVALENSelect HOST SDCLK and Driver Strength are controlled by Host Controller 0 AUTO Automatic Selection by Preset Value is Enabled 1 SLCKSEL Sampling Clock Select 7 1 SLCKSELSelect FIXED Fixed clock is used to sample data 0 TUNED Tuned clock is used to sample data 1 SDHC_HCVR Host Controller Version 0xFE 16 read-only n 0x0 0x0 SVER Spec Version 0 8 VVER Vendor Version 8 8 SDHC_MC1R MMC Control 1 0x204 8 read-write n 0x0 0x0 BOOTA e.MMC Boot Acknowledge Enable 5 1 CMDTYP e.MMC Command Type 0 2 CMDTYPSelect NORMAL Not a MMC specific command 0 WAITIRQ Wait IRQ Command 1 STREAM Stream Command 2 BOOT Boot Command 3 DDR e.MMC HSDDR Mode 3 1 FCD e.MMC Force Card Detect 7 1 OPD e.MMC Open Drain Mode 4 1 RSTN e.MMC Reset Signal 6 1 SDHC_MC2R MMC Control 2 0x205 8 write-only n 0x0 0x0 ABOOT e.MMC Abort Boot 1 1 SRESP e.MMC Abort Wait IRQ 0 1 SDHC_MCCAR Maximum Current Capabilities 0x48 32 read-only n 0x0 0x0 MAXCUR18V Maximum Current for 1.8V 16 8 MAXCUR18VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 MAXCUR30V Maximum Current for 3.0V 8 8 MAXCUR30VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 MAXCUR33V Maximum Current for 3.3V 0 8 MAXCUR33VSelect OTHER Get information via another method 0 4MA 4mA 1 8MA 8mA 2 12MA 12mA 3 SDHC_NISIER Normal Interrupt Signal Enable 0x38 16 read-write n 0x0 0x0 BLKGE Block Gap Event Signal Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Signal Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Signal Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CINS Card Insertion Signal Enable 6 1 CINSSelect MASKED Masked 0 ENABLED Enabled 1 CINT Card Interrupt Signal Enable 8 1 CINTSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Signal Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 CREM Card Removal Signal Enable 7 1 CREMSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Signal Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Signal Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_NISIER_EMMC_MODE Normal Interrupt Signal Enable NISIER 0x38 16 read-write n 0x0 0x0 BLKGE Block Gap Event Signal Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BOOTAR Boot Acknowledge Received Signal Enable 14 1 BRDRDY Buffer Read Ready Signal Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Signal Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Signal Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Signal Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Signal Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_NISTER Normal Interrupt Status Enable 0x34 16 read-write n 0x0 0x0 BLKGE Block Gap Event Status Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BRDRDY Buffer Read Ready Status Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Status Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CINS Card Insertion Status Enable 6 1 CINSSelect MASKED Masked 0 ENABLED Enabled 1 CINT Card Interrupt Status Enable 8 1 CINTSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Status Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 CREM Card Removal Status Enable 7 1 CREMSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Status Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Status Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_NISTER_EMMC_MODE Normal Interrupt Status Enable NISTER 0x34 16 read-write n 0x0 0x0 BLKGE Block Gap Event Status Enable 2 1 BLKGESelect MASKED Masked 0 ENABLED Enabled 1 BOOTAR Boot Acknowledge Received Status Enable 14 1 BRDRDY Buffer Read Ready Status Enable 5 1 BRDRDYSelect MASKED Masked 0 ENABLED Enabled 1 BWRRDY Buffer Write Ready Status Enable 4 1 BWRRDYSelect MASKED Masked 0 ENABLED Enabled 1 CMDC Command Complete Status Enable 0 1 CMDCSelect MASKED Masked 0 ENABLED Enabled 1 DMAINT DMA Interrupt Status Enable 3 1 DMAINTSelect MASKED Masked 0 ENABLED Enabled 1 TRFC Transfer Complete Status Enable 1 1 TRFCSelect MASKED Masked 0 ENABLED Enabled 1 SDHC_NISTR Normal Interrupt Status 0x30 16 read-write n 0x0 0x0 BLKGE Block Gap Event 2 1 BLKGESelect NO No Block Gap Event 0 STOP Transaction stopped at block gap 1 BRDRDY Buffer Read Ready 5 1 BRDRDYSelect NO Not ready to read buffer 0 YES Ready to read buffer 1 BWRRDY Buffer Write Ready 4 1 BWRRDYSelect NO Not ready to write buffer 0 YES Ready to write buffer 1 CINS Card Insertion 6 1 CINSSelect NO Card state stable or Debouncing 0 YES Card inserted 1 CINT Card Interrupt 8 1 CINTSelect NO No Card Interrupt 0 YES Generate Card Interrupt 1 CMDC Command Complete 0 1 CMDCSelect NO No command complete 0 YES Command complete 1 CREM Card Removal 7 1 CREMSelect NO Card state stable or Debouncing 0 YES Card Removed 1 DMAINT DMA Interrupt 3 1 DMAINTSelect NO No DMA Interrupt 0 YES DMA Interrupt is generated 1 ERRINT Error Interrupt 15 1 ERRINTSelect NO No Error 0 YES Error 1 TRFC Transfer Complete 1 1 TRFCSelect NO Not complete 0 YES Command execution is completed 1 SDHC_NISTR_EMMC_MODE Normal Interrupt Status NISTR 0x30 16 read-write n 0x0 0x0 BLKGE Block Gap Event 2 1 BLKGESelect NO No Block Gap Event 0 STOP Transaction stopped at block gap 1 BOOTAR Boot Acknowledge Received 14 1 BRDRDY Buffer Read Ready 5 1 BRDRDYSelect NO Not ready to read buffer 0 YES Ready to read buffer 1 BWRRDY Buffer Write Ready 4 1 BWRRDYSelect NO Not ready to write buffer 0 YES Ready to write buffer 1 CMDC Command Complete 0 1 CMDCSelect NO No command complete 0 YES Command complete 1 DMAINT DMA Interrupt 3 1 DMAINTSelect NO No DMA Interrupt 0 YES DMA Interrupt is generated 1 ERRINT Error Interrupt 15 1 ERRINTSelect NO No Error 0 YES Error 1 TRFC Transfer Complete 1 1 TRFCSelect NO Not complete 0 YES Command execution is completed 1 SDHC_PCR Power Control 0x29 8 read-write n 0x0 0x0 SDBPWR SD Bus Power 0 1 SDBPWRSelect OFF Power off 0 ON Power on 1 SDBVSEL SD Bus Voltage Select 1 3 SDBVSELSelect 1V8 1.8V (Typ.) 5 3V0 3.0V (Typ.) 6 3V3 3.3V (Typ.) 7 SDHC_PSR Present State 0x24 32 read-only n 0x0 0x0 BUFRDEN Buffer Read Enable 11 1 BUFRDENSelect DISABLE Read disable 0 ENABLE Read enable 1 BUFWREN Buffer Write Enable 10 1 BUFWRENSelect DISABLE Write disable 0 ENABLE Write enable 1 CARDDPL Card Detect Pin Level 18 1 CARDDPLSelect NO No card present (SDCD#=1) 0 YES Card present (SDCD#=0) 1 CARDINS Card Inserted 16 1 CARDINSSelect NO Reset or Debouncing or No Card 0 YES Card inserted 1 CARDSS Card State Stable 17 1 CARDSSSelect NO Reset or Debouncing 0 YES No Card or Insered 1 CMDINHC Command Inhibit (CMD) 0 1 CMDINHCSelect CAN Can issue command using only CMD line 0 CANNOT Cannot issue command 1 CMDINHD Command Inhibit (DAT) 1 1 CMDINHDSelect CAN Can issue command which uses the DAT line 0 CANNOT Cannot issue command which uses the DAT line 1 CMDLL CMD Line Level 24 1 DATLL DAT[3:0] Line Level 20 4 DLACT DAT Line Active 2 1 DLACTSelect INACTIVE DAT Line Inactive 0 ACTIVE DAT Line Active 1 RTACT Read Transfer Active 9 1 RTACTSelect NO No valid data 0 YES Transferring data 1 RTREQ Re-Tuning Request 3 1 RTREQSelect OK Fixed or well-tuned sampling clock 0 REQUIRED Sampling clock needs re-tuning 1 WRPPL Write Protect Pin Level 19 1 WRPPLSelect PROTECTED Write protected (SDWP#=0) 0 ENABLED Write enabled (SDWP#=1) 1 WTACT Write Transfer Active 8 1 WTACTSelect NO No valid data 0 YES Transferring data 1 SDHC_PVR[0] Preset Value n 0xC0 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[1] Preset Value n 0x122 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[2] Preset Value n 0x186 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[3] Preset Value n 0x1EC 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[4] Preset Value n 0x254 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[5] Preset Value n 0x2BE 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[6] Preset Value n 0x32A 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_PVR[7] Preset Value n 0x398 16 read-write n 0x0 0x0 CLKGSEL Clock Generator Select Value for Initialization 10 1 CLKGSELSelect DIV Host Controller Ver2.00 Compatible Clock Generator (Divider) 0 PROG Programmable Clock Generator 1 DRVSEL Driver Strength Select Value for Initialization 14 2 DRVSELSelect B Driver Type B is Selected 0 A Driver Type A is Selected 1 C Driver Type C is Selected 2 D Driver Type D is Selected 3 SDCLKFSEL SDCLK Frequency Select Value for Initialization 0 10 SDHC_RR[0] Response 0x20 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 SDHC_RR[1] Response 0x34 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 SDHC_RR[2] Response 0x4C 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 SDHC_RR[3] Response 0x68 32 read-only n 0x0 0x0 CMDRESP Command Response 0 32 SDHC_SISR Slot Interrupt Status 0xFC 16 read-only n 0x0 0x0 INTSSL Interrupt Signal for Each Slot 0 1 SDHC_SRR Software Reset 0x2F 8 read-write n 0x0 0x0 SWRSTALL Software Reset For All 0 1 SWRSTALLSelect WORK Work 0 RESET Reset 1 SWRSTCMD Software Reset For CMD Line 1 1 SWRSTCMDSelect WORK Work 0 RESET Reset 1 SWRSTDAT Software Reset For DAT Line 2 1 SWRSTDATSelect WORK Work 0 RESET Reset 1 SDHC_SSAR SDMA System Address / Argument 2 0x0 32 read-write n 0x0 0x0 ADDR SDMA System Address 0 32 SDHC_SSAR_CMD23_MODE SDMA System Address / Argument 2 SSAR 0x0 32 read-write n 0x0 0x0 ARG2 Argument 2 0 32 SDHC_TCR Timeout Control 0x2E 8 read-write n 0x0 0x0 DTCVAL Data Timeout Counter Value 0 4 SDHC_TMR Transfer Mode 0xC 16 read-write n 0x0 0x0 ACMDEN Auto Command Enable 2 2 ACMDENSelect DISABLED Auto Command Disabled 0 CMD12 Auto CMD12 Enable 1 CMD23 Auto CMD23 Enable 2 BCEN Block Count Enable 1 1 BCENSelect DISABLE Disable 0 ENABLE Enable 1 DMAEN DMA Enable 0 1 DMAENSelect DISABLE No data transfer or Non DMA data transfer 0 ENABLE DMA data transfer 1 DTDSEL Data Transfer Direction Selection 4 1 DTDSELSelect WRITE Write (Host to Card) 0 READ Read (Card to Host) 1 MSBSEL Multi/Single Block Selection 5 1 MSBSELSelect SINGLE Single Block 0 MULTIPLE Multiple Block 1 SDHC_WCR Wakeup Control 0x2B 8 read-write n 0x0 0x0 WKENCINS Wakeup Event Enable on Card Insertion 1 1 WKENCINSSelect DISABLE Disable 0 ENABLE Enable 1 WKENCINT Wakeup Event Enable on Card Interrupt 0 1 WKENCINTSelect DISABLE Disable 0 ENABLE Enable 1 WKENCREM Wakeup Event Enable on Card Removal 2 1 WKENCREMSelect DISABLE Disable 0 ENABLE Enable 1 SISR Slot Interrupt Status 0xFC 16 read-only n 0x0 0x0 INTSSL Interrupt Signal for Each Slot 0 1 SRR Software Reset 0x2F 8 read-write n 0x0 0x0 SWRSTALL Software Reset For All 0 1 SWRSTALLSelect WORK Work 0 RESET Reset 1 SWRSTCMD Software Reset For CMD Line 1 1 SWRSTCMDSelect WORK Work 0 RESET Reset 1 SWRSTDAT Software Reset For DAT Line 2 1 SWRSTDATSelect WORK Work 0 RESET Reset 1 SSAR SDMA System Address / Argument 2 0x0 32 read-write n 0x0 0x0 ADDR SDMA System Address 0 32 SSAR_CMD23_MODE SDMA System Address / Argument 2 SSAR 0x0 32 read-write n 0x0 0x0 ARG2 Argument 2 0 32 TCR Timeout Control 0x2E 8 read-write n 0x0 0x0 DTCVAL Data Timeout Counter Value 0 4 TMR Transfer Mode 0xC 16 read-write n 0x0 0x0 ACMDEN Auto Command Enable 2 2 ACMDENSelect DISABLED Auto Command Disabled 0 CMD12 Auto CMD12 Enable 1 CMD23 Auto CMD23 Enable 2 BCEN Block Count Enable 1 1 BCENSelect DISABLE Disable 0 ENABLE Enable 1 DMAEN DMA Enable 0 1 DMAENSelect DISABLE No data transfer or Non DMA data transfer 0 ENABLE DMA data transfer 1 DTDSEL Data Transfer Direction Selection 4 1 DTDSELSelect WRITE Write (Host to Card) 0 READ Read (Card to Host) 1 MSBSEL Multi/Single Block Selection 5 1 MSBSELSelect SINGLE Single Block 0 MULTIPLE Multiple Block 1 WCR Wakeup Control 0x2B 8 read-write n 0x0 0x0 WKENCINS Wakeup Event Enable on Card Insertion 1 1 WKENCINSSelect DISABLE Disable 0 ENABLE Enable 1 WKENCINT Wakeup Event Enable on Card Interrupt 0 1 WKENCINTSelect DISABLE Disable 0 ENABLE Enable 1 WKENCREM Wakeup Event Enable on Card Removal 2 1 WKENCREMSelect DISABLE Disable 0 ENABLE Enable 1 SERCOM0 Serial Communication Interface SERCOM 0x0 0x0 0x31 registers n SERCOM0_0 46 SERCOM0_1 47 SERCOM0_2 48 SERCOM0_OTHER 49 ADDR SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_INT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 ICSPACE Inter-Character Spacing 0 6 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SDASETUP SDA Setup Time 0 4 DATA USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 LENGTH USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 RXERRCNT Receive Error Count 0 8 RXPL USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0 55US 5-6 SCL Time-Out(50-60us) 1 105US 10-11 SCL Time-Out(100-110us) 2 205US 20-21 SCL Time-Out(200-210us) 3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - CTRLC I2C Master Mode - - I2CM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - CTRLC I2C Slave Mode - - I2CS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SDASETUP SDA Setup Time 0 4 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - LENGTH I2C Slave Mode - - I2CS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIM - ADDR SPI Master Mode - - SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIM - BAUD SPI Master Mode - - SPIM Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIM - CTRLA SPI Master Mode - - SPIM Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIM - CTRLB SPI Master Mode - - SPIM Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIM - CTRLC SPI Master Mode - - SPIM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIM - DATA SPI Master Mode - - SPIM Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIM - DBGCTRL SPI Master Mode - - SPIM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIM - INTENCLR SPI Master Mode - - SPIM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIM - INTENSET SPI Master Mode - - SPIM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIM - INTFLAG SPI Master Mode - - SPIM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIM - LENGTH SPI Master Mode - - SPIM Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIM - STATUS SPI Master Mode - - SPIM Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIM - SYNCBUSY SPI Master Mode - - SPIM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIS - ADDR SPI Slave Mode - - SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIS - BAUD SPI Slave Mode - - SPIS Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIS - CTRLA SPI Slave Mode - - SPIS Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIS - CTRLB SPI Slave Mode - - SPIS Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIS - CTRLC SPI Slave Mode - - SPIS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIS - DATA SPI Slave Mode - - SPIS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIS - DBGCTRL SPI Slave Mode - - SPIS Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIS - INTENCLR SPI Slave Mode - - SPIS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIS - INTENSET SPI Slave Mode - - SPIS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIS - INTFLAG SPI Slave Mode - - SPIS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIS - LENGTH SPI Slave Mode - - SPIS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIS - STATUS SPI Slave Mode - - SPIS Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIS - SYNCBUSY SPI Slave Mode - - SPIS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_EXT - BAUD USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - BAUD_FRACFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_FRAC_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_USARTFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - CTRLA USART EXTERNAL CLOCK Mode - - USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_EXT - CTRLB USART EXTERNAL CLOCK Mode - - USART_EXT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_EXT - CTRLC USART EXTERNAL CLOCK Mode - - USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_EXT - DATA USART EXTERNAL CLOCK Mode - - USART_EXT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_EXT - DBGCTRL USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_EXT - INTENCLR USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_EXT - INTENSET USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_EXT - INTFLAG USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_EXT - LENGTH USART EXTERNAL CLOCK Mode - - USART_EXT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_EXT - RXERRCNT USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_EXT - RXPL USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_EXT - STATUS USART EXTERNAL CLOCK Mode - - USART_EXT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_EXT - SYNCBUSY USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_INT - BAUD USART INTERNAL CLOCK Mode - - USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - BAUD_FRACFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_FRAC_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_USARTFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - CTRLA USART INTERNAL CLOCK Mode - - USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_INT - CTRLB USART INTERNAL CLOCK Mode - - USART_INT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_INT - CTRLC USART INTERNAL CLOCK Mode - - USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_INT - DATA USART INTERNAL CLOCK Mode - - USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_INT - DBGCTRL USART INTERNAL CLOCK Mode - - USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_INT - INTENCLR USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_INT - INTENSET USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_INT - INTFLAG USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_INT - LENGTH USART INTERNAL CLOCK Mode - - USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_INT - RXERRCNT USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_INT - RXPL USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_INT - STATUS USART INTERNAL CLOCK Mode - - USART_INT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_INT - SYNCBUSY USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 STATUS USART_INT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM1 Serial Communication Interface SERCOM 0x0 0x0 0x31 registers n SERCOM1_0 50 SERCOM1_1 51 SERCOM1_2 52 SERCOM1_OTHER 53 ADDR SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_INT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 ICSPACE Inter-Character Spacing 0 6 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SDASETUP SDA Setup Time 0 4 DATA USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 LENGTH USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 RXERRCNT Receive Error Count 0 8 RXPL USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0 55US 5-6 SCL Time-Out(50-60us) 1 105US 10-11 SCL Time-Out(100-110us) 2 205US 20-21 SCL Time-Out(200-210us) 3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - CTRLC I2C Master Mode - - I2CM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - CTRLC I2C Slave Mode - - I2CS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SDASETUP SDA Setup Time 0 4 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - LENGTH I2C Slave Mode - - I2CS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIM - ADDR SPI Master Mode - - SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIM - BAUD SPI Master Mode - - SPIM Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIM - CTRLA SPI Master Mode - - SPIM Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIM - CTRLB SPI Master Mode - - SPIM Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIM - CTRLC SPI Master Mode - - SPIM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIM - DATA SPI Master Mode - - SPIM Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIM - DBGCTRL SPI Master Mode - - SPIM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIM - INTENCLR SPI Master Mode - - SPIM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIM - INTENSET SPI Master Mode - - SPIM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIM - INTFLAG SPI Master Mode - - SPIM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIM - LENGTH SPI Master Mode - - SPIM Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIM - STATUS SPI Master Mode - - SPIM Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIM - SYNCBUSY SPI Master Mode - - SPIM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIS - ADDR SPI Slave Mode - - SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIS - BAUD SPI Slave Mode - - SPIS Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIS - CTRLA SPI Slave Mode - - SPIS Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIS - CTRLB SPI Slave Mode - - SPIS Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIS - CTRLC SPI Slave Mode - - SPIS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIS - DATA SPI Slave Mode - - SPIS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIS - DBGCTRL SPI Slave Mode - - SPIS Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIS - INTENCLR SPI Slave Mode - - SPIS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIS - INTENSET SPI Slave Mode - - SPIS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIS - INTFLAG SPI Slave Mode - - SPIS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIS - LENGTH SPI Slave Mode - - SPIS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIS - STATUS SPI Slave Mode - - SPIS Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIS - SYNCBUSY SPI Slave Mode - - SPIS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_EXT - BAUD USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - BAUD_FRACFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_FRAC_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_USARTFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - CTRLA USART EXTERNAL CLOCK Mode - - USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_EXT - CTRLB USART EXTERNAL CLOCK Mode - - USART_EXT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_EXT - CTRLC USART EXTERNAL CLOCK Mode - - USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_EXT - DATA USART EXTERNAL CLOCK Mode - - USART_EXT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_EXT - DBGCTRL USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_EXT - INTENCLR USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_EXT - INTENSET USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_EXT - INTFLAG USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_EXT - LENGTH USART EXTERNAL CLOCK Mode - - USART_EXT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_EXT - RXERRCNT USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_EXT - RXPL USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_EXT - STATUS USART EXTERNAL CLOCK Mode - - USART_EXT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_EXT - SYNCBUSY USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_INT - BAUD USART INTERNAL CLOCK Mode - - USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - BAUD_FRACFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_FRAC_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_USARTFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - CTRLA USART INTERNAL CLOCK Mode - - USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_INT - CTRLB USART INTERNAL CLOCK Mode - - USART_INT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_INT - CTRLC USART INTERNAL CLOCK Mode - - USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_INT - DATA USART INTERNAL CLOCK Mode - - USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_INT - DBGCTRL USART INTERNAL CLOCK Mode - - USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_INT - INTENCLR USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_INT - INTENSET USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_INT - INTFLAG USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_INT - LENGTH USART INTERNAL CLOCK Mode - - USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_INT - RXERRCNT USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_INT - RXPL USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_INT - STATUS USART INTERNAL CLOCK Mode - - USART_INT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_INT - SYNCBUSY USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 STATUS USART_INT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM2 Serial Communication Interface SERCOM 0x0 0x0 0x31 registers n SERCOM2_0 54 SERCOM2_1 55 SERCOM2_2 56 SERCOM2_OTHER 57 ADDR SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_INT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 ICSPACE Inter-Character Spacing 0 6 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SDASETUP SDA Setup Time 0 4 DATA USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 LENGTH USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 RXERRCNT Receive Error Count 0 8 RXPL USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0 55US 5-6 SCL Time-Out(50-60us) 1 105US 10-11 SCL Time-Out(100-110us) 2 205US 20-21 SCL Time-Out(200-210us) 3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - CTRLC I2C Master Mode - - I2CM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - CTRLC I2C Slave Mode - - I2CS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SDASETUP SDA Setup Time 0 4 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - LENGTH I2C Slave Mode - - I2CS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIM - ADDR SPI Master Mode - - SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIM - BAUD SPI Master Mode - - SPIM Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIM - CTRLA SPI Master Mode - - SPIM Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIM - CTRLB SPI Master Mode - - SPIM Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIM - CTRLC SPI Master Mode - - SPIM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIM - DATA SPI Master Mode - - SPIM Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIM - DBGCTRL SPI Master Mode - - SPIM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIM - INTENCLR SPI Master Mode - - SPIM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIM - INTENSET SPI Master Mode - - SPIM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIM - INTFLAG SPI Master Mode - - SPIM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIM - LENGTH SPI Master Mode - - SPIM Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIM - STATUS SPI Master Mode - - SPIM Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIM - SYNCBUSY SPI Master Mode - - SPIM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIS - ADDR SPI Slave Mode - - SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIS - BAUD SPI Slave Mode - - SPIS Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIS - CTRLA SPI Slave Mode - - SPIS Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIS - CTRLB SPI Slave Mode - - SPIS Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIS - CTRLC SPI Slave Mode - - SPIS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIS - DATA SPI Slave Mode - - SPIS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIS - DBGCTRL SPI Slave Mode - - SPIS Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIS - INTENCLR SPI Slave Mode - - SPIS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIS - INTENSET SPI Slave Mode - - SPIS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIS - INTFLAG SPI Slave Mode - - SPIS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIS - LENGTH SPI Slave Mode - - SPIS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIS - STATUS SPI Slave Mode - - SPIS Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIS - SYNCBUSY SPI Slave Mode - - SPIS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_EXT - BAUD USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - BAUD_FRACFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_FRAC_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_USARTFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - CTRLA USART EXTERNAL CLOCK Mode - - USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_EXT - CTRLB USART EXTERNAL CLOCK Mode - - USART_EXT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_EXT - CTRLC USART EXTERNAL CLOCK Mode - - USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_EXT - DATA USART EXTERNAL CLOCK Mode - - USART_EXT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_EXT - DBGCTRL USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_EXT - INTENCLR USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_EXT - INTENSET USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_EXT - INTFLAG USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_EXT - LENGTH USART EXTERNAL CLOCK Mode - - USART_EXT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_EXT - RXERRCNT USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_EXT - RXPL USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_EXT - STATUS USART EXTERNAL CLOCK Mode - - USART_EXT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_EXT - SYNCBUSY USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_INT - BAUD USART INTERNAL CLOCK Mode - - USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - BAUD_FRACFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_FRAC_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_USARTFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - CTRLA USART INTERNAL CLOCK Mode - - USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_INT - CTRLB USART INTERNAL CLOCK Mode - - USART_INT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_INT - CTRLC USART INTERNAL CLOCK Mode - - USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_INT - DATA USART INTERNAL CLOCK Mode - - USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_INT - DBGCTRL USART INTERNAL CLOCK Mode - - USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_INT - INTENCLR USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_INT - INTENSET USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_INT - INTFLAG USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_INT - LENGTH USART INTERNAL CLOCK Mode - - USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_INT - RXERRCNT USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_INT - RXPL USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_INT - STATUS USART INTERNAL CLOCK Mode - - USART_INT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_INT - SYNCBUSY USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 STATUS USART_INT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM3 Serial Communication Interface SERCOM 0x0 0x0 0x31 registers n SERCOM3_0 58 SERCOM3_1 59 SERCOM3_2 60 SERCOM3_OTHER 61 ADDR SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_INT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 ICSPACE Inter-Character Spacing 0 6 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SDASETUP SDA Setup Time 0 4 DATA USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 LENGTH USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 RXERRCNT Receive Error Count 0 8 RXPL USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0 55US 5-6 SCL Time-Out(50-60us) 1 105US 10-11 SCL Time-Out(100-110us) 2 205US 20-21 SCL Time-Out(200-210us) 3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - CTRLC I2C Master Mode - - I2CM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - CTRLC I2C Slave Mode - - I2CS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SDASETUP SDA Setup Time 0 4 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - LENGTH I2C Slave Mode - - I2CS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIM - ADDR SPI Master Mode - - SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIM - BAUD SPI Master Mode - - SPIM Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIM - CTRLA SPI Master Mode - - SPIM Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIM - CTRLB SPI Master Mode - - SPIM Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIM - CTRLC SPI Master Mode - - SPIM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIM - DATA SPI Master Mode - - SPIM Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIM - DBGCTRL SPI Master Mode - - SPIM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIM - INTENCLR SPI Master Mode - - SPIM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIM - INTENSET SPI Master Mode - - SPIM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIM - INTFLAG SPI Master Mode - - SPIM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIM - LENGTH SPI Master Mode - - SPIM Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIM - STATUS SPI Master Mode - - SPIM Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIM - SYNCBUSY SPI Master Mode - - SPIM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIS - ADDR SPI Slave Mode - - SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIS - BAUD SPI Slave Mode - - SPIS Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIS - CTRLA SPI Slave Mode - - SPIS Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIS - CTRLB SPI Slave Mode - - SPIS Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIS - CTRLC SPI Slave Mode - - SPIS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIS - DATA SPI Slave Mode - - SPIS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIS - DBGCTRL SPI Slave Mode - - SPIS Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIS - INTENCLR SPI Slave Mode - - SPIS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIS - INTENSET SPI Slave Mode - - SPIS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIS - INTFLAG SPI Slave Mode - - SPIS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIS - LENGTH SPI Slave Mode - - SPIS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIS - STATUS SPI Slave Mode - - SPIS Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIS - SYNCBUSY SPI Slave Mode - - SPIS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_EXT - BAUD USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - BAUD_FRACFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_FRAC_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_USARTFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - CTRLA USART EXTERNAL CLOCK Mode - - USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_EXT - CTRLB USART EXTERNAL CLOCK Mode - - USART_EXT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_EXT - CTRLC USART EXTERNAL CLOCK Mode - - USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_EXT - DATA USART EXTERNAL CLOCK Mode - - USART_EXT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_EXT - DBGCTRL USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_EXT - INTENCLR USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_EXT - INTENSET USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_EXT - INTFLAG USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_EXT - LENGTH USART EXTERNAL CLOCK Mode - - USART_EXT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_EXT - RXERRCNT USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_EXT - RXPL USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_EXT - STATUS USART EXTERNAL CLOCK Mode - - USART_EXT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_EXT - SYNCBUSY USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_INT - BAUD USART INTERNAL CLOCK Mode - - USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - BAUD_FRACFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_FRAC_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_USARTFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - CTRLA USART INTERNAL CLOCK Mode - - USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_INT - CTRLB USART INTERNAL CLOCK Mode - - USART_INT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_INT - CTRLC USART INTERNAL CLOCK Mode - - USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_INT - DATA USART INTERNAL CLOCK Mode - - USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_INT - DBGCTRL USART INTERNAL CLOCK Mode - - USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_INT - INTENCLR USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_INT - INTENSET USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_INT - INTFLAG USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_INT - LENGTH USART INTERNAL CLOCK Mode - - USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_INT - RXERRCNT USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_INT - RXPL USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_INT - STATUS USART INTERNAL CLOCK Mode - - USART_INT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_INT - SYNCBUSY USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 STATUS USART_INT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM4 Serial Communication Interface SERCOM 0x0 0x0 0x31 registers n SERCOM4_0 62 SERCOM4_1 63 SERCOM4_2 64 SERCOM4_OTHER 65 ADDR SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_INT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 ICSPACE Inter-Character Spacing 0 6 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SDASETUP SDA Setup Time 0 4 DATA USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 LENGTH USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 RXERRCNT Receive Error Count 0 8 RXPL USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0 55US 5-6 SCL Time-Out(50-60us) 1 105US 10-11 SCL Time-Out(100-110us) 2 205US 20-21 SCL Time-Out(200-210us) 3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - CTRLC I2C Master Mode - - I2CM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - CTRLC I2C Slave Mode - - I2CS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SDASETUP SDA Setup Time 0 4 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - LENGTH I2C Slave Mode - - I2CS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIM - ADDR SPI Master Mode - - SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIM - BAUD SPI Master Mode - - SPIM Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIM - CTRLA SPI Master Mode - - SPIM Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIM - CTRLB SPI Master Mode - - SPIM Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIM - CTRLC SPI Master Mode - - SPIM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIM - DATA SPI Master Mode - - SPIM Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIM - DBGCTRL SPI Master Mode - - SPIM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIM - INTENCLR SPI Master Mode - - SPIM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIM - INTENSET SPI Master Mode - - SPIM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIM - INTFLAG SPI Master Mode - - SPIM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIM - LENGTH SPI Master Mode - - SPIM Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIM - STATUS SPI Master Mode - - SPIM Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIM - SYNCBUSY SPI Master Mode - - SPIM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIS - ADDR SPI Slave Mode - - SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIS - BAUD SPI Slave Mode - - SPIS Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIS - CTRLA SPI Slave Mode - - SPIS Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIS - CTRLB SPI Slave Mode - - SPIS Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIS - CTRLC SPI Slave Mode - - SPIS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIS - DATA SPI Slave Mode - - SPIS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIS - DBGCTRL SPI Slave Mode - - SPIS Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIS - INTENCLR SPI Slave Mode - - SPIS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIS - INTENSET SPI Slave Mode - - SPIS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIS - INTFLAG SPI Slave Mode - - SPIS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIS - LENGTH SPI Slave Mode - - SPIS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIS - STATUS SPI Slave Mode - - SPIS Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIS - SYNCBUSY SPI Slave Mode - - SPIS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_EXT - BAUD USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - BAUD_FRACFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_FRAC_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_USARTFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - CTRLA USART EXTERNAL CLOCK Mode - - USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_EXT - CTRLB USART EXTERNAL CLOCK Mode - - USART_EXT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_EXT - CTRLC USART EXTERNAL CLOCK Mode - - USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_EXT - DATA USART EXTERNAL CLOCK Mode - - USART_EXT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_EXT - DBGCTRL USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_EXT - INTENCLR USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_EXT - INTENSET USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_EXT - INTFLAG USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_EXT - LENGTH USART EXTERNAL CLOCK Mode - - USART_EXT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_EXT - RXERRCNT USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_EXT - RXPL USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_EXT - STATUS USART EXTERNAL CLOCK Mode - - USART_EXT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_EXT - SYNCBUSY USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_INT - BAUD USART INTERNAL CLOCK Mode - - USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - BAUD_FRACFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_FRAC_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_USARTFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - CTRLA USART INTERNAL CLOCK Mode - - USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_INT - CTRLB USART INTERNAL CLOCK Mode - - USART_INT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_INT - CTRLC USART INTERNAL CLOCK Mode - - USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_INT - DATA USART INTERNAL CLOCK Mode - - USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_INT - DBGCTRL USART INTERNAL CLOCK Mode - - USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_INT - INTENCLR USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_INT - INTENSET USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_INT - INTFLAG USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_INT - LENGTH USART INTERNAL CLOCK Mode - - USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_INT - RXERRCNT USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_INT - RXPL USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_INT - STATUS USART INTERNAL CLOCK Mode - - USART_INT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_INT - SYNCBUSY USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 STATUS USART_INT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM5 Serial Communication Interface SERCOM 0x0 0x0 0x31 registers n SERCOM5_0 66 SERCOM5_1 67 SERCOM5_2 68 SERCOM5_OTHER 69 ADDR SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 GENCEN General Call Address Enable 0 1 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 BAUD USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 BAUD_FRACFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_FRAC_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 BAUD_USARTFP_MODE USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 CTRLA USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0x0 SYNC Synchronous Communication 0x1 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0x0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 0x1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0x0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 0x1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0x0 PAD1 SERCOM PAD[1] is used as data input 0x1 PAD2 SERCOM PAD[2] is used as data input 0x2 PAD3 SERCOM PAD[3] is used as data input 0x3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0x0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 0x2 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0x0 LSB LSB is transmitted first 0x1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0x0 USART_FRAME_NO_PARITY USART frame 0x0 USART_FRAME_WITH_PARITY USART frame with parity 0x1 SPI_FRAME_WITH_ADDR SPI Frame with Addr 0x2 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 0x2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud (LIN Slave) - break detection and auto-baud 0x4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 0x5 USART_FRAME_ISO_7816 ISO 7816 0x7 IBON Immediate Buffer Overflow Notification 8 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0x0 55US 5-6 SCL Time-Out(50-60us) 0x1 105US 10-11 SCL Time-Out(100-110us) 0x2 205US 20-21 SCL Time-Out(200-210us) 0x3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0x0 USART_INT_CLK USART with internal clock 0x1 SPI_SLAVE SPI in slave operation 0x2 SPI_MASTER SPI in master operation 0x3 I2C_SLAVE I2C slave operation 0x4 I2C_MASTER I2C master operation 0x5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0x0 PAD1 SERCOM PAD[1] is used for data reception 0x1 PAD2 SERCOM PAD[2] is used for data reception 0x2 PAD3 SERCOM PAD[3] is used for data reception 0x3 SAMPA Sample Adjustment 22 2 SAMPASelect ADJ0 16x Over-sampling = 7-8-9 8x Over-sampling = 3-4-5 0x0 ADJ1 16x Over-sampling = 9-10-11 8x Over-sampling = 4-5-6 0x1 ADJ2 16x Over-sampling = 11-12-13 8x Over-sampling = 5-6-7 0x2 ADJ3 16x Over-sampling = 13-14-15 8x Over-sampling = 6-7-8 0x3 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0x0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 0x1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 0x2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 0x3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 0x4 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0x0 75NS 50-100ns hold time 0x1 450NS 300-600ns hold time 0x2 600NS 400-800ns hold time 0x3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0x0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 0x1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 0x2 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 PAD[0] = TxD PAD[1] = XCK 0x0 PAD2 PAD[0] = TxD PAD[2] = RTS PAD[3] = CTS 0x2 PAD3 PAD[0] = TxD PAD[1] = XCK PAD[2] = TE 0x3 CTRLB USART_INT Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0x0 2_ADDRESSES Two unique Addressess 0x1 RANGE Address Range 0x2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0x0 9_BIT 9 Bits 0x1 5_BIT 5 Bits 0x5 6_BIT 6 Bits 0x6 7_BIT 7 Bits 0x7 CMD Command 16 2 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 GCMD PMBus Group Command 9 1 LINCMD LIN Command 24 2 LINCMDSelect NONE Normal USART transmission 0x0 SOFTWARE_CONTROL_TRANSMIT_CMD Break field is transmitted when DATA is written 0x1 AUTO_TRANSMIT_CMD Break, sync and identifier are automatically transmitted when DATA is written with the identifier 0x2 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0x0 ODD Odd Parity 0x1 QCEN Quick Command Enable 9 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0x0 2_BIT Two Stop Bits 0x1 SFDE Start of Frame Detection Enable 9 1 SMEN Smart Mode Enable 8 1 SSDE Slave Select Low Detect Enable 9 1 TXEN Transmitter Enable 16 1 CTRLC USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 BRKLENSelect 13_BIT Break field transmission is 13 bit times 0x0 17_BIT Break field transmission is 17 bit times 0x1 21_BIT Break field transmission is 21 bit times 0x2 26_BIT Break field transmission is 26 bit times 0x3 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0x0 DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0x0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 0x1 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 0x1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 0x2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 0x3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 HDRDLYSelect DELAY0 Delay between break and sync transmission is 1 bit time Delay between sync and ID transmission is 1 bit time 0x0 DELAY1 Delay between break and sync transmission is 4 bit time Delay between sync and ID transmission is 4 bit time 0x1 DELAY2 Delay between break and sync transmission is 8 bit time Delay between sync and ID transmission is 4 bit time 0x2 DELAY3 Delay between break and sync transmission is 14 bit time Delay between sync and ID transmission is 4 bit time 0x3 ICSPACE Inter-Character Spacing 0 6 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SDASETUP SDA Setup Time 0 4 DATA USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 DBGCTRL USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 INTENCLR USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRDY Data Interrupt Disable 2 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 PREC Stop Received Interrupt Disable 0 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 SB Slave On Bus Interrupt Disable 1 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 INTENSET USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRDY Data Interrupt Enable 2 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 PREC Stop Received Interrupt Enable 0 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 SB Slave On Bus Interrupt Enable 1 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 INTFLAG USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 CTSIC Clear To Send Input Change Interrupt 4 1 DRDY Data Interrupt 2 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 PREC Stop Received Interrupt 0 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 SB Slave On Bus Interrupt 1 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 LENGTH USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 RXERRCNT USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 RXERRCNT Receive Error Count 0 8 RXPL USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_I2CM - ADDR I2C Master Mode - - I2CM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 11 HS High Speed Mode 14 1 LEN Length 16 8 LENEN Length Enable 13 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CM - BAUD I2C Master Mode - - I2CM Baud Rate 0xC 32 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 BAUDLOW Baud Rate Value Low 8 8 HSBAUD High Speed Baud Rate Value 16 8 HSBAUDLOW High Speed Baud Rate Value Low 24 8 SERCOM_I2CM - CTRLA I2C Master Mode - - I2CM Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 INACTOUT Inactive Time-Out 28 2 INACTOUTSelect DISABLE Disabled 0 55US 5-6 SCL Time-Out(50-60us) 1 105US 10-11 SCL Time-Out(100-110us) 2 205US 20-21 SCL Time-Out(200-210us) 3 LOWTOUTEN SCL Low Timeout Enable 30 1 MEXTTOEN Master SCL Low Extend Timeout 22 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run in Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CM - CTRLB I2C Master Mode - - I2CM Control B 0x4 32 read-write n 0x0 0x0 ACKACT Acknowledge Action 18 1 CMD Command 16 2 QCEN Quick Command Enable 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CM - CTRLC I2C Master Mode - - I2CM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SERCOM_I2CM - DATA I2C Master Mode - - I2CM Data 0x28 8 read-write n 0x0 0x0 DATA Data Value 0 8 SERCOM_I2CM - DBGCTRL I2C Master Mode - - I2CM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_I2CM - INTENCLR I2C Master Mode - - I2CM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Disable 7 1 MB Master On Bus Interrupt Disable 0 1 SB Slave On Bus Interrupt Disable 1 1 SERCOM_I2CM - INTENSET I2C Master Mode - - I2CM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt Enable 7 1 MB Master On Bus Interrupt Enable 0 1 SB Slave On Bus Interrupt Enable 1 1 SERCOM_I2CM - INTFLAG I2C Master Mode - - I2CM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 ERROR Combined Error Interrupt 7 1 MB Master On Bus Interrupt 0 1 SB Slave On Bus Interrupt 1 1 SERCOM_I2CM - STATUS I2C Master Mode - - I2CM Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 LENERR Length Error 10 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SERCOM_I2CM - SYNCBUSY I2C Master Mode - - I2CM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SERCOM_I2CS - ADDR I2C Slave Mode - - I2CS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 1 10 ADDRMASK Address Mask 17 10 GENCEN General Call Address Enable 0 1 TENBITEN Ten Bit Addressing Enable 15 1 SERCOM_I2CS - CTRLA I2C Slave Mode - - I2CS Control A 0x0 32 read-write n 0x0 0x0 ENABLE Enable 1 1 LOWTOUTEN SCL Low Timeout Enable 30 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 PINOUT Pin Usage 16 1 RUNSTDBY Run during Standby 7 1 SCLSM SCL Clock Stretch Mode 27 1 SDAHOLD SDA Hold Time 20 2 SDAHOLDSelect DISABLE Disabled 0 75NS 50-100ns hold time 1 450NS 300-600ns hold time 2 600NS 400-800ns hold time 3 SEXTTOEN Slave SCL Low Extend Timeout 23 1 SPEED Transfer Speed 24 2 SPEEDSelect STANDARD_AND_FAST_MODE Standard Mode(Sm) Upto 100kHz and Fast Mode(Fm) Upto 400kHz 0 FASTPLUS_MODE Fast-mode Plus Upto 1MHz 1 HIGH_SPEED_MODE High-speed mode Upto 3.4MHz 2 SWRST Software Reset 0 1 SERCOM_I2CS - CTRLB I2C Slave Mode - - I2CS Control B 0x4 32 read-write n 0x0 0x0 AACKEN Automatic Address Acknowledge 10 1 ACKACT Acknowledge Action 18 1 AMODE Address Mode 14 2 CMD Command 16 2 GCMD PMBus Group Command 9 1 SMEN Smart Mode Enable 8 1 SERCOM_I2CS - CTRLC I2C Slave Mode - - I2CS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Data transaction from/to DATA register are 8-bit 0 DATA_TRANS_32BIT Data transaction from/to DATA register are 32-bit 1 SDASETUP SDA Setup Time 0 4 SERCOM_I2CS - DATA I2C Slave Mode - - I2CS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_I2CS - INTENCLR I2C Slave Mode - - I2CS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Disable 1 1 DRDY Data Interrupt Disable 2 1 ERROR Combined Error Interrupt Disable 7 1 PREC Stop Received Interrupt Disable 0 1 SERCOM_I2CS - INTENSET I2C Slave Mode - - I2CS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt Enable 1 1 DRDY Data Interrupt Enable 2 1 ERROR Combined Error Interrupt Enable 7 1 PREC Stop Received Interrupt Enable 0 1 SERCOM_I2CS - INTFLAG I2C Slave Mode - - I2CS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 AMATCH Address Match Interrupt 1 1 DRDY Data Interrupt 2 1 ERROR Combined Error Interrupt 7 1 PREC Stop Received Interrupt 0 1 SERCOM_I2CS - LENGTH I2C Slave Mode - - I2CS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_I2CS - STATUS I2C Slave Mode - - I2CS Status 0x1A 16 read-write n 0x0 0x0 BUSERR Bus Error 0 1 CLKHOLD Clock Hold 7 1 COLL Transmit Collision 1 1 DIR Read/Write Direction 3 1 HS High Speed 10 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 SERCOM_I2CS - SYNCBUSY I2C Slave Mode - - I2CS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH Length Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIM - ADDR SPI Master Mode - - SPIM Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIM - BAUD SPI Master Mode - - SPIM Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIM - CTRLA SPI Master Mode - - SPIM Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIM - CTRLB SPI Master Mode - - SPIM Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIM - CTRLC SPI Master Mode - - SPIM Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIM - DATA SPI Master Mode - - SPIM Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIM - DBGCTRL SPI Master Mode - - SPIM Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIM - INTENCLR SPI Master Mode - - SPIM Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIM - INTENSET SPI Master Mode - - SPIM Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIM - INTFLAG SPI Master Mode - - SPIM Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIM - LENGTH SPI Master Mode - - SPIM Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIM - STATUS SPI Master Mode - - SPIM Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIM - SYNCBUSY SPI Master Mode - - SPIM Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_SPIS - ADDR SPI Slave Mode - - SPIS Address 0x24 32 read-write n 0x0 0x0 ADDR Address Value 0 8 ADDRMASK Address Mask 16 8 SERCOM_SPIS - BAUD SPI Slave Mode - - SPIS Baud Rate 0xC 8 read-write n 0x0 0x0 BAUD Baud Rate Value 0 8 SERCOM_SPIS - CTRLA SPI Slave Mode - - SPIS Control A 0x0 32 read-write n 0x0 0x0 CPHA Clock Phase 28 1 CPHASelect LEADING_EDGE The data is sampled on a leading SCK edge and changed on a trailing SCK edge 0 TRAILING_EDGE The data is sampled on a trailing SCK edge and changed on a leading SCK edge 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW SCK is low when idle 0 IDLE_HIGH SCK is high when idle 1 DIPO Data In Pinout 20 2 DIPOSelect PAD0 SERCOM PAD[0] is used as data input 0 PAD1 SERCOM PAD[1] is used as data input 1 PAD2 SERCOM PAD[2] is used as data input 2 PAD3 SERCOM PAD[3] is used as data input 3 DOPO Data Out Pinout 16 2 DOPOSelect PAD0 DO on PAD[0], SCK on PAD[1] and SS on PAD[2] 0 PAD2 DO on PAD[3], SCK on PAD[1] and SS on PAD[2] 2 DORD Data Order 30 1 DORDSelect MSB MSB is transferred first 0 LSB LSB is transferred first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect SPI_FRAME SPI Frame 0 SPI_FRAME_WITH_ADDR SPI Frame with Addr 2 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 SWRST Software Reset 0 1 SERCOM_SPIS - CTRLB SPI Slave Mode - - SPIS Control B 0x4 32 read-write n 0x0 0x0 AMODE Address Mode 14 2 AMODESelect MASK SPI Address mask 0 2_ADDRESSES Two unique Addressess 1 RANGE Address Range 2 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 bits 0 9_BIT 9 bits 1 MSSEN Master Slave Select Enable 13 1 PLOADEN Data Preload Enable 6 1 RXEN Receiver Enable 17 1 SSDE Slave Select Low Detect Enable 9 1 SERCOM_SPIS - CTRLC SPI Slave Mode - - SPIS Control C 0x8 32 read-write n 0x0 0x0 DATA32B Data 32 Bit 24 1 DATA32BSelect DATA_TRANS_8BIT Transaction from and to DATA register are 8-bit 0 DATA_TRANS_32BIT Transaction from and to DATA register are 32-bit 1 ICSPACE Inter-Character Spacing 0 6 SERCOM_SPIS - DATA SPI Slave Mode - - SPIS Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_SPIS - DBGCTRL SPI Slave Mode - - SPIS Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_SPIS - INTENCLR SPI Slave Mode - - SPIS Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXC Receive Complete Interrupt Disable 2 1 SSL Slave Select Low Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_SPIS - INTENSET SPI Slave Mode - - SPIS Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXC Receive Complete Interrupt Enable 2 1 SSL Slave Select Low Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_SPIS - INTFLAG SPI Slave Mode - - SPIS Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXC Receive Complete Interrupt 2 1 SSL Slave Select Low Interrupt Flag 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_SPIS - LENGTH SPI Slave Mode - - SPIS Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 1 SERCOM_SPIS - STATUS SPI Slave Mode - - SPIS Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 LENERR Transaction Length Error 11 1 SERCOM_SPIS - SYNCBUSY SPI Slave Mode - - SPIS Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_EXT - BAUD USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - BAUD_FRACFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_FRAC_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_EXT - BAUD_USARTFP_MODE USART EXTERNAL CLOCK Mode - - USART_EXT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_EXT - CTRLA USART EXTERNAL CLOCK Mode - - USART_EXT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_EXT - CTRLB USART EXTERNAL CLOCK Mode - - USART_EXT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_EXT - CTRLC USART EXTERNAL CLOCK Mode - - USART_EXT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_EXT - DATA USART EXTERNAL CLOCK Mode - - USART_EXT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_EXT - DBGCTRL USART EXTERNAL CLOCK Mode - - USART_EXT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_EXT - INTENCLR USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_EXT - INTENSET USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_EXT - INTFLAG USART EXTERNAL CLOCK Mode - - USART_EXT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_EXT - LENGTH USART EXTERNAL CLOCK Mode - - USART_EXT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_EXT - RXERRCNT USART EXTERNAL CLOCK Mode - - USART_EXT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_EXT - RXPL USART EXTERNAL CLOCK Mode - - USART_EXT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_EXT - STATUS USART EXTERNAL CLOCK Mode - - USART_EXT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_EXT - SYNCBUSY USART EXTERNAL CLOCK Mode - - USART_EXT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SERCOM_USART_INT - BAUD USART INTERNAL CLOCK Mode - - USART_INT Baud Rate 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - BAUD_FRACFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_FRAC_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 13 FP Fractional Part 13 3 SERCOM_USART_INT - BAUD_USARTFP_MODE USART INTERNAL CLOCK Mode - - USART_INT Baud Rate BAUD 0xC 16 read-write n 0x0 0x0 BAUD Baud Rate Value 0 16 SERCOM_USART_INT - CTRLA USART INTERNAL CLOCK Mode - - USART_INT Control A 0x0 32 read-write n 0x0 0x0 CMODE Communication Mode 28 1 CMODESelect ASYNC Asynchronous Communication 0 SYNC Synchronous Communication 1 CPOL Clock Polarity 29 1 CPOLSelect IDLE_LOW TxD Change:- Rising XCK edge, RxD Sample:- Falling XCK edge 0 IDLE_HIGH TxD Change:- Falling XCK edge, RxD Sample:- Rising XCK edge 1 DORD Data Order 30 1 DORDSelect MSB MSB is transmitted first 0 LSB LSB is transmitted first 1 ENABLE Enable 1 1 FORM Frame Format 24 4 FORMSelect USART_FRAME_NO_PARITY USART frame 0 USART_FRAME_WITH_PARITY USART frame with parity 1 USART_FRAME_LIN_MASTER_MODE LIN Master - Break and sync generation 2 USART_FRAME_AUTO_BAUD_NO_PARITY Auto-baud - break detection and auto-baud 4 USART_FRAME_AUTO_BAUD_WITH_PARITY Auto-baud - break detection and auto-baud with parity 5 USART_FRAME_ISO_7816 ISO 7816 7 IBON Immediate Buffer Overflow Notification 8 1 MODE Operating Mode 2 3 MODESelect USART_EXT_CLK USART with external clock 0 USART_INT_CLK USART with internal clock 1 SPI_SLAVE SPI in slave operation 2 SPI_MASTER SPI in master operation 3 I2C_SLAVE I2C slave operation 4 I2C_MASTER I2C master operation 5 RUNSTDBY Run during Standby 7 1 RXINV Receive Data Invert 10 1 RXPO Receive Data Pinout 20 2 RXPOSelect PAD0 SERCOM PAD[0] is used for data reception 0 PAD1 SERCOM PAD[1] is used for data reception 1 PAD2 SERCOM PAD[2] is used for data reception 2 PAD3 SERCOM PAD[3] is used for data reception 3 SAMPA Sample Adjustment 22 2 SAMPR Sample 13 3 SAMPRSelect 16X_ARITHMETIC 16x over-sampling using arithmetic baudrate generation 0 16X_FRACTIONAL 16x over-sampling using fractional baudrate generation 1 8X_ARITHMETIC 8x over-sampling using arithmetic baudrate generation 2 8X_FRACTIONAL 8x over-sampling using fractional baudrate generation 3 3X_ARITHMETIC 3x over-sampling using arithmetic baudrate generation 4 SWRST Software Reset 0 1 TXINV Transmit Data Invert 9 1 TXPO Transmit Data Pinout 16 2 TXPOSelect PAD0 SERCOM PAD[0] is used for data transmission 0 PAD3 SERCOM_PAD[0] is used for data transmission 3 SERCOM_USART_INT - CTRLB USART INTERNAL CLOCK Mode - - USART_INT Control B 0x4 32 read-write n 0x0 0x0 CHSIZE Character Size 0 3 CHSIZESelect 8_BIT 8 Bits 0 9_BIT 9 Bits 1 5_BIT 5 Bits 5 6_BIT 6 Bits 6 7_BIT 7 Bits 7 COLDEN Collision Detection Enable 8 1 ENC Encoding Format 10 1 LINCMD LIN Command 24 2 PMODE Parity Mode 13 1 PMODESelect EVEN Even Parity 0 ODD Odd Parity 1 RXEN Receiver Enable 17 1 SBMODE Stop Bit Mode 6 1 SBMODESelect 1_BIT One Stop Bit 0 2_BIT Two Stop Bits 1 SFDE Start of Frame Detection Enable 9 1 TXEN Transmitter Enable 16 1 SERCOM_USART_INT - CTRLC USART INTERNAL CLOCK Mode - - USART_INT Control C 0x8 32 read-write n 0x0 0x0 BRKLEN LIN Master Break Length 8 2 DATA32B Data 32 Bit 24 2 DATA32BSelect DATA_READ_WRITE_CHSIZE Data reads and writes according CTRLB.CHSIZE 0 DATA_READ_CHSIZE_WRITE_32BIT Data reads according CTRLB.CHSIZE and writes according 32-bit extension 1 DATA_READ_32BIT_WRITE_CHSIZE Data reads according 32-bit extension and writes according CTRLB.CHSIZE 2 DATA_READ_WRITE_32BIT Data reads and writes according 32-bit extension 3 DSNACK Disable Successive NACK 17 1 GTIME Guard Time 0 3 HDRDLY LIN Master Header Delay 10 2 INACK Inhibit Not Acknowledge 16 1 MAXITER Maximum Iterations 20 3 SERCOM_USART_INT - DATA USART INTERNAL CLOCK Mode - - USART_INT Data 0x28 32 read-write n 0x0 0x0 DATA Data Value 0 32 SERCOM_USART_INT - DBGCTRL USART INTERNAL CLOCK Mode - - USART_INT Debug Control 0x30 8 read-write n 0x0 0x0 DBGSTOP Debug Mode 0 1 SERCOM_USART_INT - INTENCLR USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Clear 0x14 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Disable 4 1 DRE Data Register Empty Interrupt Disable 0 1 ERROR Combined Error Interrupt Disable 7 1 RXBRK Break Received Interrupt Disable 5 1 RXC Receive Complete Interrupt Disable 2 1 RXS Receive Start Interrupt Disable 3 1 TXC Transmit Complete Interrupt Disable 1 1 SERCOM_USART_INT - INTENSET USART INTERNAL CLOCK Mode - - USART_INT Interrupt Enable Set 0x16 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt Enable 4 1 DRE Data Register Empty Interrupt Enable 0 1 ERROR Combined Error Interrupt Enable 7 1 RXBRK Break Received Interrupt Enable 5 1 RXC Receive Complete Interrupt Enable 2 1 RXS Receive Start Interrupt Enable 3 1 TXC Transmit Complete Interrupt Enable 1 1 SERCOM_USART_INT - INTFLAG USART INTERNAL CLOCK Mode - - USART_INT Interrupt Flag Status and Clear 0x18 8 read-write n 0x0 0x0 CTSIC Clear To Send Input Change Interrupt 4 1 DRE Data Register Empty Interrupt 0 1 ERROR Combined Error Interrupt 7 1 RXBRK Break Received Interrupt 5 1 RXC Receive Complete Interrupt 2 1 RXS Receive Start Interrupt 3 1 TXC Transmit Complete Interrupt 1 1 SERCOM_USART_INT - LENGTH USART INTERNAL CLOCK Mode - - USART_INT Length 0x22 16 read-write n 0x0 0x0 LEN Data Length 0 8 LENEN Data Length Enable 8 2 SERCOM_USART_INT - RXERRCNT USART INTERNAL CLOCK Mode - - USART_INT Receive Error Count 0x20 8 read-only n 0x0 0x0 SERCOM_USART_INT - RXPL USART INTERNAL CLOCK Mode - - USART_INT Receive Pulse Length 0xE 8 read-write n 0x0 0x0 RXPL Receive Pulse Length 0 8 SERCOM_USART_INT - STATUS USART INTERNAL CLOCK Mode - - USART_INT Status 0x1A 16 read-write n 0x0 0x0 BUFOVF Buffer Overflow 2 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 FERR Frame Error 1 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 PERR Parity Error 0 1 TXE Transmitter Empty 6 1 SERCOM_USART_INT - SYNCBUSY USART INTERNAL CLOCK Mode - - USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 STATUS USART_INT Status 0x1A 16 read-write n 0x0 0x0 ARBLOST Arbitration Lost 1 1 BUFOVF Buffer Overflow 2 1 BUSERR Bus Error 0 1 BUSSTATE Bus State 4 2 CLKHOLD Clock Hold 7 1 COLL Collision Detected 5 1 CTS Clear To Send 3 1 DIR Read/Write Direction 3 1 FERR Frame Error 1 1 HS High Speed 10 1 ISF Inconsistent Sync Field 4 1 ITER Maximum Number of Repetitions Reached 7 1 LENERR Transaction Length Error 11 1 LOWTOUT SCL Low Timeout 6 1 MEXTTOUT Master SCL Low Extend Timeout 8 1 PERR Parity Error 0 1 RXNACK Received Not Acknowledge 2 1 SEXTTOUT Slave SCL Low Extend Timeout 9 1 SR Repeated Start 4 1 TXE Transmitter Empty 6 1 SYNCBUSY USART_INT Synchronization Busy 0x1C 32 read-only n 0x0 0x0 CTRLB CTRLB Synchronization Busy 2 1 ENABLE SERCOM Enable Synchronization Busy 1 1 LENGTH LENGTH Synchronization Busy 4 1 RXERRCNT RXERRCNT Synchronization Busy 3 1 SWRST Software Reset Synchronization Busy 0 1 SYSOP System Operation Synchronization Busy 2 1 SUPC Supply Controller SUPC 0x0 0x0 0x2C registers n SUPC_OTHER 8 SUPC_BODDET 9 BBPS Battery Backup Power Switch 0x20 32 read-write n 0x0 0x0 CONF Battery Backup Configuration 0 1 CONFSelect BOD33 The power switch is handled by the BOD33 0 FORCED In Backup Domain, the backup domain is always supplied by battery backup power 1 WAKEEN Wake Enable 2 1 BKIN Backup Input Control 0x28 32 read-only n 0x0 0x0 BKIN0 Backup Input 0 0 1 BKIN1 Backup Input 1 1 1 BKOUT Backup Output Control 0x24 32 read-write n 0x0 0x0 CLROUT0 Clear OUT0 8 1 CLROUT1 Clear OUT1 9 1 ENOUT0 Enable OUT0 0 1 ENOUT1 Enable OUT1 1 1 RTCTGLOUT0 RTC Toggle OUT0 24 1 RTCTGLOUT1 RTC Toggle OUT1 25 1 SETOUT0 Set OUT0 16 1 SETOUT1 Set OUT1 17 1 BOD33 BOD33 Control 0x10 32 read-write n 0x0 0x0 ACTION Action when Threshold Crossed 2 2 ACTIONSelect NONE No action 0 RESET The BOD33 generates a reset 1 INT The BOD33 generates an interrupt 2 BKUP The BOD33 puts the device in backup sleep mode 3 ENABLE Enable 1 1 HYST Hysteresis value 8 4 LEVEL Threshold Level for VDD 16 8 PSEL Prescaler Select 12 3 PSELSelect NODIV Not divided 0 DIV4 Divide clock by 4 1 DIV8 Divide clock by 8 2 DIV16 Divide clock by 16 3 DIV32 Divide clock by 32 4 DIV64 Divide clock by 64 5 DIV128 Divide clock by 128 6 DIV256 Divide clock by 256 7 RUNBKUP Run in Backup mode 7 1 RUNHIB Run in Hibernate mode 6 1 RUNSTDBY Run in Standby mode 5 1 STDBYCFG Configuration in Standby mode 4 1 VBATLEVEL Threshold Level in battery backup sleep mode for VBAT 24 8 INTENCLR Interrupt Enable Clear 0x0 32 read-write n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 2 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 INTENSET Interrupt Enable Set 0x4 32 read-write n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 2 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 INTFLAG Interrupt Flag Status and Clear 0x8 32 read-write n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 2 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 STATUS Power and Clocks Status 0xC 32 read-only n 0x0 0x0 B33SRDY BOD33 Synchronization Ready 2 1 BOD33DET BOD33 Detection 1 1 BOD33RDY BOD33 Ready 0 1 VCORERDY VDDCORE Ready 10 1 VREGRDY Voltage Regulator Ready 8 1 VREF VREF Control 0x1C 32 read-write n 0x0 0x0 ONDEMAND On Demand Contrl 7 1 RUNSTDBY Run during Standby 6 1 SEL Voltage Reference Selection 16 4 SELSelect 1V0 1.0V voltage reference typical value 0 1V1 1.1V voltage reference typical value 1 1V2 1.2V voltage reference typical value 2 1V25 1.25V voltage reference typical value 3 2V0 2.0V voltage reference typical value 4 2V2 2.2V voltage reference typical value 5 2V4 2.4V voltage reference typical value 6 2V5 2.5V voltage reference typical value 7 TSEN Temperature Sensor Output Enable 1 1 TSSEL Temperature Sensor Selection 3 1 VREFOE Voltage Reference Output Enable 2 1 VREG VREG Control 0x18 32 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNBKUP Run in Backup mode 7 1 SEL Voltage Regulator Selection 2 1 SELSelect LDO LDO selection 0 BUCK Buck selection 1 VSEN Voltage Scaling Enable 16 1 VSPER Voltage Scaling Period 24 3 SystemControl System Control Registers SystemControl 0x0 0x0 0xD8C registers n ACTLR Auxiliary Control Register 0x8 32 read-write n 0x0 0x0 DISDEFWBUF Disable wruite buffer use during default memory map accesses 1 1 DISFOLD Disable IT folding 2 1 DISFPCA Disable automatic update of CONTROL.FPCA 8 1 DISMCYCINT Disable interruption of LDM/STM instructions 0 1 DISOOFP Disable out-of-order FP instructions 9 1 ADR Auxiliary Feature Register 0xD4C 32 read-only n 0x0 0x0 AFSR Auxiliary Fault Status Register 0xD3C 32 read-write n 0x0 0x0 IMPDEF AUXFAULT input signals 0 32 AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0x0 0x0 ENDIANNESS Data endianness, 0=little, 1=big 15 1 ENDIANNESSSelect VALUE_0 Little-endian 0 VALUE_1 Big-endian 1 PRIGROUP Interrupt priority grouping 8 3 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect VALUE_0 No system reset request 0 VALUE_1 Asserts a signal to the outer system that requests a reset 1 VECTCLRACTIVE Must write 0 1 1 VECTKEY Register key 16 16 VECTRESET Must write 0 0 1 BFAR BusFault Address Register 0xD38 32 read-write n 0x0 0x0 ADDRESS Address that generated the BusFault 0 32 CCR Configuration and Control Register 0xD14 32 read-write n 0x0 0x0 BFHFNMIGN Ignore LDM/STM BusFault for -1/-2 priority handlers 8 1 DIV_0_TRP Enables divide by 0 trap 4 1 NONBASETHRDENA Indicates how processor enters Thread mode 0 1 STKALIGN Indicates stack alignment on exception entry 9 1 STKALIGNSelect VALUE_0 4-byte aligned 0 VALUE_1 8-byte aligned 1 UNALIGN_TRP Enables unaligned access traps 3 1 UNALIGN_TRPSelect VALUE_0 Do not trap unaligned halfword and word accesses 0 VALUE_1 Trap unaligned halfword and word accesses 1 USERSETMPEND Enables unprivileged software access to STIR register 1 1 CFSR Configurable Fault Status Register 0xD28 32 read-write n 0x0 0x0 BFARVALID BusFault Address Register valid 15 1 DACCVIOL Data access violation 1 1 DIVBYZERO Divide by zero UsageFault 25 1 IACCVIOL Instruction access violation 0 1 IBUSERR Instruction bus error 8 1 IMPRECISERR Imprecise data bus error 10 1 INVPC Invalid PC load UsageFault 18 1 INVSTATE Invalid state UsageFault 17 1 LSPERR BusFault occured during FP lazy state preservation 13 1 MLSPERR MemManager Fault occured during FP lazy state preservation 5 1 MMARVALID MemManage Fault Address Register valid 7 1 MSTKERR MemManage Fault on stacking for exception entry 4 1 MUNSTKERR MemManage Fault on unstacking for exception return 3 1 NOCP No coprocessor UsageFault 19 1 PRECISERR Precise data bus error 9 1 STKERR BusFault on stacking for exception entry 12 1 UNALIGNED Unaligned access UsageFault 24 1 UNDEFINSTR Undefined instruction UsageFault 16 1 UNSTKERR BusFault on unstacking for exception return 11 1 CPACR Coprocessor Access Control Register 0xD88 32 read-write n 0x0 0x0 CP10 Access privileges for coprocessor 10 20 2 CP10Select DENIED Access denied 0 PRIV Privileged access only 1 FULL Full access 3 CP11 Access privileges for coprocessor 11 22 2 CP11Select DENIED Access denied 0 PRIV Privileged access only 1 FULL Full access 3 CPUID CPUID Base Register 0xD00 32 read-only n 0x0 0x0 CONSTANT Constant 16 4 IMPLEMENTER Implementer code, 0x41=ARM 24 8 PARTNO Process Part Number, 0xC24=Cortex-M4 4 12 REVISION Processor revision number 0 4 VARIANT Variant number 20 4 DFR Debug Feature Register 0xD48 32 read-only n 0x0 0x0 DFSR Debug Fault Status Register 0xD30 32 read-write n 0x0 0x0 BKPT 1 1 DWTTRAP 2 1 EXTERNAL 4 1 HALTED 0 1 VCATCH 3 1 HFSR HardFault Status Register 0xD2C 32 read-write n 0x0 0x0 DEBUGEVT Debug: always write 0 31 1 FORCED Forced Hard Fault 30 1 VECTTBL BusFault on a Vector Table read during exception processing 1 1 ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING Interrupt pending flag 22 1 ISRPREEMPT Debug only 23 1 NMIPENDSET NMI set-pending bit 31 1 NMIPENDSETSelect VALUE_0 Write: no effect; read: NMI exception is not pending 0 VALUE_1 Write: changes NMI exception state to pending; read: NMI exception is pending 1 PENDSTCLR SysTick clear-pending bit 25 1 PENDSTCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the SysTick exception 1 PENDSTSET SysTick set-pending bit 26 1 PENDSTSETSelect VALUE_0 Write: no effect; read: SysTick exception is not pending 0 VALUE_1 Write: changes SysTick exception state to pending; read: SysTick exception is pending 1 PENDSVCLR PendSV clear-pending bit 27 1 PENDSVCLRSelect VALUE_0 No effect 0 VALUE_1 Removes the pending state from the PendSV exception 1 PENDSVSET PendSV set-pending bit 28 1 PENDSVSETSelect VALUE_0 Write: no effect; read: PendSV exception is not pending 0 VALUE_1 Write: changes PendSV exception state to pending; read: PendSV exception is pending 1 RETTOBASE No preempted active exceptions to execute 11 1 VECTACTIVE Active exception number 0 9 VECTPENDING Exception number of the highest priority pending enabled exception 12 6 ICTR Interrupt Controller Type Register 0x4 32 read-only n 0x0 0x0 INTLINESNUM 0 4 ISAR0 Instruction Set Attributes Register 0xD60 32 read-only n 0x0 0x0 ISAR1 Instruction Set Attributes Register 0xD64 32 read-only n 0x0 0x0 ISAR2 Instruction Set Attributes Register 0xD68 32 read-only n 0x0 0x0 ISAR3 Instruction Set Attributes Register 0xD6C 32 read-only n 0x0 0x0 ISAR4 Instruction Set Attributes Register 0xD70 32 read-only n 0x0 0x0 ISAR[0] Instruction Set Attributes Register 0x1AC0 32 read-only n 0x0 0x0 ISAR[1] Instruction Set Attributes Register 0x2824 32 read-only n 0x0 0x0 ISAR[2] Instruction Set Attributes Register 0x358C 32 read-only n 0x0 0x0 ISAR[3] Instruction Set Attributes Register 0x42F8 32 read-only n 0x0 0x0 ISAR[4] Instruction Set Attributes Register 0x5068 32 read-only n 0x0 0x0 MMFAR MemManage Fault Address Register 0xD34 32 read-write n 0x0 0x0 ADDRESS Address that generated the MemManage fault 0 32 MMFR0 Memory Model Feature Register 0xD50 32 read-only n 0x0 0x0 MMFR1 Memory Model Feature Register 0xD54 32 read-only n 0x0 0x0 MMFR2 Memory Model Feature Register 0xD58 32 read-only n 0x0 0x0 MMFR3 Memory Model Feature Register 0xD5C 32 read-only n 0x0 0x0 MMFR[0] Memory Model Feature Register 0x1AA0 32 read-only n 0x0 0x0 MMFR[1] Memory Model Feature Register 0x27F4 32 read-only n 0x0 0x0 MMFR[2] Memory Model Feature Register 0x354C 32 read-only n 0x0 0x0 MMFR[3] Memory Model Feature Register 0x42A8 32 read-only n 0x0 0x0 PFR0 Processor Feature Register 0xD40 32 read-write n 0x0 0x0 PFR1 Processor Feature Register 0xD44 32 read-write n 0x0 0x0 PFR[0] Processor Feature Register 0x1A80 32 read-write n 0x0 0x0 PFR[1] Processor Feature Register 0x27C4 32 read-write n 0x0 0x0 SCR System Control Register 0xD10 32 read-write n 0x0 0x0 SEVONPEND Send Event on Pending bit 4 1 SEVONPENDSelect VALUE_0 Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 Enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 SLEEPDEEP Deep Sleep used as low power mode 2 1 SLEEPDEEPSelect VALUE_0 Sleep 0 VALUE_1 Deep sleep 1 SLEEPONEXIT Sleep-on-exit on handler return 1 1 SLEEPONEXITSelect VALUE_0 Do not sleep when returning to Thread mode 0 VALUE_1 Enter sleep, or deep sleep, on return from an ISR 1 SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 BUSFAULTACT BusFault exception active bit 1 1 BUSFAULTENA BusFault enable bit 17 1 BUSFAULTPENDED BusFault exception pending bit 14 1 MEMFAULTACT MemManage exception active bit 0 1 MEMFAULTENA MemManage enable bit 16 1 MEMFAULTPENDED MemManage exception pending bit 13 1 MONITORACT DebugMonitor exception active bit 8 1 PENDSVACT PendSV exception active bit 10 1 SVCALLACT SVCall active bit 7 1 SVCALLPENDED SVCall pending bit 15 1 SYSTICKACT SysTick exception active bit 11 1 USGFAULTACT UsageFault exception active bit 3 1 USGFAULTENA UsageFault enable bit 18 1 USGFAULTPENDED UsageFault exception pending bit 12 1 SHPR1 System Handler Priority Register 1 0xD18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 PRI_5 Priority of system handler 5, BusFault 8 8 PRI_6 Priority of system handler 6, UsageFault 16 8 SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick exception 24 8 VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0x0 TBLOFF Vector table base offset 7 25 SysTick System timer SysTick 0x0 0x0 0x10 registers n CALIB SysTick Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF No Separate Reference Clock 31 1 NOREFSelect VALUE_0 The reference clock is provided 0 VALUE_1 The reference clock is not provided 1 SKEW TENMS is rounded from non-integer ratio 30 1 SKEWSelect VALUE_0 10ms calibration value is exact 0 VALUE_1 10ms calibration value is inexact, because of the clock frequency 1 TENMS Reload value to use for 10ms timing 0 24 CSR SysTick Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Clock Source 0=external, 1=processor 2 1 CLKSOURCESelect VALUE_0 External clock 0 VALUE_1 Processor clock 1 COUNTFLAG Timer counted to 0 since last read of register 16 1 ENABLE SysTick Counter Enable 0 1 ENABLESelect VALUE_0 Counter disabled 0 VALUE_1 Counter enabled 1 TICKINT SysTick Exception Request Enable 1 1 TICKINTSelect VALUE_0 Counting down to 0 does not assert the SysTick exception request 0 VALUE_1 Counting down to 0 asserts the SysTick exception request 1 CVR SysTick Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 RVR SysTick Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 TC0 Basic Timer Counter TC 0x0 0x0 0x38 registers n TC0 107 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CCBUF[0] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF[1] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CC[0] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC[1] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT32 - CCBUF[0] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF[1] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CC[0] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC[1] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT8 - CCBUF[0] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF[1] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CC[0] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC[1] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC1 Basic Timer Counter TC 0x0 0x0 0x38 registers n TC1 108 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CCBUF[0] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF[1] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CC[0] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC[1] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT32 - CCBUF[0] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF[1] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CC[0] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC[1] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT8 - CCBUF[0] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF[1] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CC[0] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC[1] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC2 Basic Timer Counter TC 0x0 0x0 0x38 registers n TC2 109 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CCBUF[0] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF[1] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CC[0] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC[1] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT32 - CCBUF[0] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF[1] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CC[0] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC[1] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT8 - CCBUF[0] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF[1] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CC[0] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC[1] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC3 Basic Timer Counter TC 0x0 0x0 0x38 registers n TC3 110 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CCBUF[0] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF[1] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CC[0] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC[1] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT32 - CCBUF[0] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF[1] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CC[0] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC[1] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT8 - CCBUF[0] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF[1] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CC[0] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC[1] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC4 Basic Timer Counter TC 0x0 0x0 0x38 registers n TC4 111 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CCBUF[0] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF[1] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CC[0] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC[1] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT32 - CCBUF[0] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF[1] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CC[0] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC[1] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT8 - CCBUF[0] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF[1] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CC[0] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC[1] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC5 Basic Timer Counter TC 0x0 0x0 0x38 registers n TC5 112 CC0 COUNT32 Compare and Capture 0x1C 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CC1 COUNT32 Compare and Capture 0x20 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 CCBUF0 COUNT32 Compare and Capture Buffer 0x30 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 CCBUF1 COUNT32 Compare and Capture Buffer 0x34 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 COUNT COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 DBGCTRL Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 DRVCTRL Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 EVCTRL Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 PER COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 PERBUF COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 STATUS Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 SYNCBUSY Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - CCBUF[0] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x60 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CCBUF[1] 16-bit Counter Mode - - COUNT16 Compare and Capture Buffer 0x92 16 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 16 TC_COUNT16 - CC[0] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x38 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - CC[1] 16-bit Counter Mode - - COUNT16 Compare and Capture 0x56 16 read-write n 0x0 0x0 CC Counter/Compare Value 0 16 TC_COUNT16 - COUNT 16-bit Counter Mode - - COUNT16 Count 0x14 16 read-write n 0x0 0x0 COUNT Counter Value 0 16 TC_COUNT16 - CTRLA 16-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT16 - CTRLBCLR 16-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - CTRLBSET 16-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT16 - DBGCTRL 16-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT16 - DRVCTRL 16-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT16 - EVCTRL 16-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT16 - INTENCLR 16-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT16 - INTENSET 16-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT16 - INTFLAG 16-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT16 - STATUS 16-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT16 - SYNCBUSY 16-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT16 - WAVE 16-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT32 - CCBUF[0] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x60 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CCBUF[1] 32-bit Counter Mode - - COUNT32 Compare and Capture Buffer 0x94 32 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 32 TC_COUNT32 - CC[0] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x38 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - CC[1] 32-bit Counter Mode - - COUNT32 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Counter/Compare Value 0 32 TC_COUNT32 - COUNT 32-bit Counter Mode - - COUNT32 Count 0x14 32 read-write n 0x0 0x0 COUNT Counter Value 0 32 TC_COUNT32 - CTRLA 32-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT32 - CTRLBCLR 32-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - CTRLBSET 32-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT32 - DBGCTRL 32-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT32 - DRVCTRL 32-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT32 - EVCTRL 32-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT32 - INTENCLR 32-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT32 - INTENSET 32-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT32 - INTFLAG 32-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT32 - STATUS 32-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT32 - SYNCBUSY 32-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT32 - WAVE 32-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TC_COUNT8 - CCBUF[0] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x60 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CCBUF[1] 8-bit Counter Mode - - COUNT8 Compare and Capture Buffer 0x91 8 read-write n 0x0 0x0 CCBUF Counter/Compare Buffer Value 0 8 TC_COUNT8 - CC[0] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x38 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - CC[1] 8-bit Counter Mode - - COUNT8 Compare and Capture 0x55 8 read-write n 0x0 0x0 CC Counter/Compare Value 0 8 TC_COUNT8 - COUNT 8-bit Counter Mode - - COUNT8 Count 0x14 8 read-write n 0x0 0x0 COUNT Counter Value 0 8 TC_COUNT8 - CTRLA 8-bit Counter Mode - - Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 11 1 CAPTEN0 Capture Channel 0 Enable 16 1 CAPTEN1 Capture Channel 1 Enable 17 1 CAPTMODE0 Capture Mode Channel 0 24 2 CAPTMODE0Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 CAPTMODE1 Capture mode Channel 1 27 2 CAPTMODE1Select DEFAULT Default capture 0 CAPTMIN Minimum capture 1 CAPTMAX Maximum capture 2 COPEN0 Capture On Pin 0 Enable 20 1 COPEN1 Capture On Pin 1 Enable 21 1 ENABLE Enable 1 1 MODE Timer Counter Mode 2 2 MODESelect COUNT16 Counter in 16-bit mode 0 COUNT8 Counter in 8-bit mode 1 COUNT32 Counter in 32-bit mode 2 ONDEMAND Clock On Demand 7 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 Prescaler: GCLK_TC 0 DIV2 Prescaler: GCLK_TC/2 1 DIV4 Prescaler: GCLK_TC/4 2 DIV8 Prescaler: GCLK_TC/8 3 DIV16 Prescaler: GCLK_TC/16 4 DIV64 Prescaler: GCLK_TC/64 5 DIV256 Prescaler: GCLK_TC/256 6 DIV1024 Prescaler: GCLK_TC/1024 7 PRESCSYNC Prescaler and Counter Synchronization 4 2 PRESCSYNCSelect GCLK Reload or reset the counter on next generic clock 0 PRESC Reload or reset the counter on next prescaler clock 1 RESYNC Reload or reset the counter on next generic clock and reset the prescaler counter 2 RUNSTDBY Run during Standby 6 1 SWRST Software Reset 0 1 TC_COUNT8 - CTRLBCLR 8-bit Counter Mode - - Control B Clear 0x4 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - CTRLBSET 8-bit Counter Mode - - Control B Set 0x5 8 read-write n 0x0 0x0 CMD Command 5 3 CMDSelect NONE No action 0 RETRIGGER Force a start, restart or retrigger 1 STOP Force a stop 2 UPDATE Force update of double-buffered register 3 READSYNC Force a read synchronization of COUNT 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 LUPD Lock Update 1 1 ONESHOT One-Shot on Counter 2 1 TC_COUNT8 - DBGCTRL 8-bit Counter Mode - - Debug Control 0xF 8 read-write n 0x0 0x0 DBGRUN Run During Debug 0 1 TC_COUNT8 - DRVCTRL 8-bit Counter Mode - - Control C 0xD 8 read-write n 0x0 0x0 INVEN0 Output Waveform Invert Enable 0 0 1 INVEN1 Output Waveform Invert Enable 1 1 1 TC_COUNT8 - EVCTRL 8-bit Counter Mode - - Event Control 0x6 16 read-write n 0x0 0x0 EVACT Event Action 0 3 EVACTSelect OFF Event action disabled 0 RETRIGGER Start, restart or retrigger TC on event 1 COUNT Count on event 2 START Start TC on event 3 STAMP Time stamp capture 4 PPW Period catured in CC0, pulse width in CC1 5 PWP Period catured in CC1, pulse width in CC0 6 PW Pulse width capture 7 MCEO0 MC Event Output Enable 0 12 1 MCEO1 MC Event Output Enable 1 13 1 OVFEO Event Output Enable 8 1 TCEI TC Event Enable 5 1 TCINV TC Event Input Polarity 4 1 TC_COUNT8 - INTENCLR 8-bit Counter Mode - - Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 ERR ERR Interrupt Disable 1 1 MC0 MC Interrupt Disable 0 4 1 MC1 MC Interrupt Disable 1 5 1 OVF OVF Interrupt Disable 0 1 TC_COUNT8 - INTENSET 8-bit Counter Mode - - Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 ERR ERR Interrupt Enable 1 1 MC0 MC Interrupt Enable 0 4 1 MC1 MC Interrupt Enable 1 5 1 OVF OVF Interrupt Enable 0 1 TC_COUNT8 - INTFLAG 8-bit Counter Mode - - Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 ERR ERR Interrupt Flag 1 1 MC0 MC Interrupt Flag 0 4 1 MC1 MC Interrupt Flag 1 5 1 OVF OVF Interrupt Flag 0 1 TC_COUNT8 - PER 8-bit Counter Mode - - COUNT8 Period 0x1B 8 read-write n 0x0 0x0 PER Period Value 0 8 TC_COUNT8 - PERBUF 8-bit Counter Mode - - COUNT8 Period Buffer 0x2F 8 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 8 TC_COUNT8 - STATUS 8-bit Counter Mode - - Status 0xB 8 read-write n 0x0 0x0 CCBUFV0 Compare channel buffer 0 valid 4 1 CCBUFV1 Compare channel buffer 1 valid 5 1 PERBUFV Synchronization Busy Status 3 1 SLAVE Slave Status Flag 1 1 STOP Stop Status Flag 0 1 TC_COUNT8 - SYNCBUSY 8-bit Counter Mode - - Synchronization Status 0x10 32 read-only n 0x0 0x0 CC0 Compare Channel 0 6 1 CC1 Compare Channel 1 7 1 COUNT Counter 4 1 CTRLB CTRLB 2 1 ENABLE enable 1 1 PER Period 5 1 STATUS STATUS 3 1 SWRST swrst 0 1 TC_COUNT8 - WAVE 8-bit Counter Mode - - Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 WAVE Waveform Generation Control 0xC 8 read-write n 0x0 0x0 WAVEGEN Waveform Generation Mode 0 2 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 MPWM Match PWM 3 TCC0 Timer Counter Control TCC 0x0 0x0 0x88 registers n TCC0_OTHER 85 TCC0_MC0 86 TCC0_MC1 87 TCC0_MC2 88 TCC0_MC3 89 TCC0_MC4 90 TCC0_MC5 91 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC4 Compare and Capture 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC5 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF4 Compare and Capture Buffer 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF5 Compare and Capture Buffer 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CCBUF[0] Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[1] Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[2] Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[3] Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[4] Compare and Capture Buffer 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[5] Compare and Capture Buffer 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF_DITH4_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH5_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH6_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CC[0] Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[1] Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[2] Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[3] Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[4] Compare and Capture 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[5] Compare and Capture 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC_DITH4_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH5_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH6_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC1 Timer Counter Control TCC 0x0 0x0 0x88 registers n TCC1_OTHER 92 TCC1_MC0 93 TCC1_MC1 94 TCC1_MC2 95 TCC1_MC3 96 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC4 Compare and Capture 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC5 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF4 Compare and Capture Buffer 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF5 Compare and Capture Buffer 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CCBUF[0] Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[1] Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[2] Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[3] Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[4] Compare and Capture Buffer 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[5] Compare and Capture Buffer 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF_DITH4_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH5_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH6_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CC[0] Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[1] Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[2] Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[3] Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[4] Compare and Capture 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[5] Compare and Capture 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC_DITH4_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH5_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH6_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC2 Timer Counter Control TCC 0x0 0x0 0x88 registers n TCC2_OTHER 97 TCC2_MC0 98 TCC2_MC1 99 TCC2_MC2 100 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC4 Compare and Capture 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC5 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF4 Compare and Capture Buffer 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF5 Compare and Capture Buffer 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CCBUF[0] Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[1] Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[2] Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[3] Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[4] Compare and Capture Buffer 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[5] Compare and Capture Buffer 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF_DITH4_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH5_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH6_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CC[0] Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[1] Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[2] Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[3] Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[4] Compare and Capture 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[5] Compare and Capture 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC_DITH4_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH5_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH6_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC3 Timer Counter Control TCC 0x0 0x0 0x88 registers n TCC3_OTHER 101 TCC3_MC0 102 TCC3_MC1 103 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC4 Compare and Capture 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC5 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF4 Compare and Capture Buffer 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF5 Compare and Capture Buffer 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CCBUF[0] Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[1] Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[2] Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[3] Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[4] Compare and Capture Buffer 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[5] Compare and Capture Buffer 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF_DITH4_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH5_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH6_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CC[0] Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[1] Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[2] Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[3] Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[4] Compare and Capture 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[5] Compare and Capture 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC_DITH4_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH5_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH6_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TCC4 Timer Counter Control TCC 0x0 0x0 0x88 registers n TCC4_OTHER 104 TCC4_MC0 105 TCC4_MC1 106 CC0 Compare and Capture 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC1 Compare and Capture 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC2 Compare and Capture 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC3 Compare and Capture 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC4 Compare and Capture 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CC5 Compare and Capture 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 CCBUF0 Compare and Capture Buffer 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF1 Compare and Capture Buffer 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF2 Compare and Capture Buffer 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF3 Compare and Capture Buffer 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF4 Compare and Capture Buffer 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF5 Compare and Capture Buffer 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 CCBUF_DITH4_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH4_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 CCBUF_DITH5_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH5_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 CCBUF_DITH6_MODE0 Compare and Capture Buffer CCBUF[%s] 0x70 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE1 Compare and Capture Buffer CCBUF[%s] 0x74 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE2 Compare and Capture Buffer CCBUF[%s] 0x78 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE3 Compare and Capture Buffer CCBUF[%s] 0x7C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE4 Compare and Capture Buffer CCBUF[%s] 0x80 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CCBUF_DITH6_MODE5 Compare and Capture Buffer CCBUF[%s] 0x84 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 CC_DITH4_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH4_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 CC_DITH5_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH5_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 CC_DITH6_MODE0 Compare and Capture CC[%s] 0x44 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE1 Compare and Capture CC[%s] 0x48 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE2 Compare and Capture CC[%s] 0x4C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE3 Compare and Capture CC[%s] 0x50 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE4 Compare and Capture CC[%s] 0x54 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 CC_DITH6_MODE5 Compare and Capture CC[%s] 0x58 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_CCBUF[0] Compare and Capture Buffer 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[1] Compare and Capture Buffer 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[2] Compare and Capture Buffer 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[3] Compare and Capture Buffer 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[4] Compare and Capture Buffer 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF[5] Compare and Capture Buffer 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 24 TCC_CCBUF_DITH4_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH4_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 0 4 DITHERBUF Dithering Buffer Cycle Number 4 20 TCC_CCBUF_DITH5_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH5_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 5 19 DITHERBUF Dithering Buffer Cycle Number 0 5 TCC_CCBUF_DITH6_MODE[0] Compare and Capture Buffer CCBUF[%s] 0xE0 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[1] Compare and Capture Buffer CCBUF[%s] 0x154 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[2] Compare and Capture Buffer CCBUF[%s] 0x1CC 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[3] Compare and Capture Buffer CCBUF[%s] 0x248 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[4] Compare and Capture Buffer CCBUF[%s] 0x2C8 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CCBUF_DITH6_MODE[5] Compare and Capture Buffer CCBUF[%s] 0x34C 32 read-write n 0x0 0x0 CCBUF Channel Compare/Capture Buffer Value 6 18 DITHERBUF Dithering Buffer Cycle Number 0 6 TCC_CC[0] Compare and Capture 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[1] Compare and Capture 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[2] Compare and Capture 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[3] Compare and Capture 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[4] Compare and Capture 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC[5] Compare and Capture 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 0 24 TCC_CC_DITH4_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH4_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 4 20 DITHER Dithering Cycle Number 0 4 TCC_CC_DITH5_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH5_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 5 19 DITHER Dithering Cycle Number 0 5 TCC_CC_DITH6_MODE[0] Compare and Capture CC[%s] 0x88 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[1] Compare and Capture CC[%s] 0xD0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[2] Compare and Capture CC[%s] 0x11C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[3] Compare and Capture CC[%s] 0x16C 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[4] Compare and Capture CC[%s] 0x1C0 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_CC_DITH6_MODE[5] Compare and Capture CC[%s] 0x218 32 read-write n 0x0 0x0 CC Channel Compare/Capture Value 6 18 DITHER Dithering Cycle Number 0 6 TCC_COUNT Count 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 0 24 TCC_COUNT_DITH4_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 4 20 TCC_COUNT_DITH5_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 5 19 TCC_COUNT_DITH6_MODE Count COUNT 0x34 32 read-write n 0x0 0x0 COUNT Counter Value 6 18 TCC_CTRLA Control A 0x0 32 read-write n 0x0 0x0 ALOCK Auto Lock 14 1 CPTEN0 Capture Channel 0 Enable 24 1 CPTEN1 Capture Channel 1 Enable 25 1 CPTEN2 Capture Channel 2 Enable 26 1 CPTEN3 Capture Channel 3 Enable 27 1 CPTEN4 Capture Channel 4 Enable 28 1 CPTEN5 Capture Channel 5 Enable 29 1 DMAOS DMA One-shot Trigger Mode 23 1 ENABLE Enable 1 1 MSYNC Master Synchronization (only for TCC Slave Instance) 15 1 PRESCALER Prescaler 8 3 PRESCALERSelect DIV1 No division 0 DIV2 Divide by 2 1 DIV4 Divide by 4 2 DIV8 Divide by 8 3 DIV16 Divide by 16 4 DIV64 Divide by 64 5 DIV256 Divide by 256 6 DIV1024 Divide by 1024 7 PRESCSYNC Prescaler and Counter Synchronization Selection 12 2 PRESCSYNCSelect GCLK Reload or reset counter on next GCLK 0 PRESC Reload or reset counter on next prescaler clock 1 RESYNC Reload or reset counter on next GCLK and reset prescaler counter 2 RESOLUTION Enhanced Resolution 5 2 RESOLUTIONSelect NONE Dithering is disabled 0 DITH4 Dithering is done every 16 PWM frames 1 DITH5 Dithering is done every 32 PWM frames 2 DITH6 Dithering is done every 64 PWM frames 3 RUNSTDBY Run in Standby 11 1 SWRST Software Reset 0 1 TCC_CTRLBCLR Control B Clear 0x4 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_CTRLBSET Control B Set 0x5 8 read-write n 0x0 0x0 CMD TCC Command 5 3 CMDSelect NONE No action 0 RETRIGGER Clear start, restart or retrigger 1 STOP Force stop 2 UPDATE Force update or double buffered registers 3 READSYNC Force COUNT read synchronization 4 DMAOS One-shot DMA trigger 5 DIR Counter Direction 0 1 IDXCMD Ramp Index Command 3 2 IDXCMDSelect DISABLE Command disabled: Index toggles between cycles A and B 0 SET Set index: cycle B will be forced in the next cycle 1 CLEAR Clear index: cycle A will be forced in the next cycle 2 HOLD Hold index: the next cycle will be the same as the current cycle 3 LUPD Lock Update 1 1 ONESHOT One-Shot 2 1 TCC_DBGCTRL Debug Control 0x1E 8 read-write n 0x0 0x0 DBGRUN Debug Running Mode 0 1 FDDBD Fault Detection on Debug Break Detection 2 1 TCC_DRVCTRL Driver Control 0x18 32 read-write n 0x0 0x0 FILTERVAL0 Non-Recoverable Fault Input 0 Filter Value 24 4 FILTERVAL1 Non-Recoverable Fault Input 1 Filter Value 28 4 INVEN0 Output Waveform 0 Inversion 16 1 INVEN1 Output Waveform 1 Inversion 17 1 INVEN2 Output Waveform 2 Inversion 18 1 INVEN3 Output Waveform 3 Inversion 19 1 INVEN4 Output Waveform 4 Inversion 20 1 INVEN5 Output Waveform 5 Inversion 21 1 INVEN6 Output Waveform 6 Inversion 22 1 INVEN7 Output Waveform 7 Inversion 23 1 NRE0 Non-Recoverable State 0 Output Enable 0 1 NRE1 Non-Recoverable State 1 Output Enable 1 1 NRE2 Non-Recoverable State 2 Output Enable 2 1 NRE3 Non-Recoverable State 3 Output Enable 3 1 NRE4 Non-Recoverable State 4 Output Enable 4 1 NRE5 Non-Recoverable State 5 Output Enable 5 1 NRE6 Non-Recoverable State 6 Output Enable 6 1 NRE7 Non-Recoverable State 7 Output Enable 7 1 NRV0 Non-Recoverable State 0 Output Value 8 1 NRV1 Non-Recoverable State 1 Output Value 9 1 NRV2 Non-Recoverable State 2 Output Value 10 1 NRV3 Non-Recoverable State 3 Output Value 11 1 NRV4 Non-Recoverable State 4 Output Value 12 1 NRV5 Non-Recoverable State 5 Output Value 13 1 NRV6 Non-Recoverable State 6 Output Value 14 1 NRV7 Non-Recoverable State 7 Output Value 15 1 TCC_EVCTRL Event Control 0x20 32 read-write n 0x0 0x0 CNTEO Timer/counter Output Event Enable 10 1 CNTSEL Timer/counter Output Event Mode 6 2 CNTSELSelect START An interrupt/event is generated when a new counter cycle starts 0 END An interrupt/event is generated when a counter cycle ends 1 BETWEEN An interrupt/event is generated when a counter cycle ends, except for the first and last cycles 2 BOUNDARY An interrupt/event is generated when a new counter cycle starts or a counter cycle ends 3 EVACT0 Timer/counter Input Event0 Action 0 3 EVACT0Select OFF Event action disabled 0 RETRIGGER Start, restart or re-trigger counter on event 1 COUNTEV Count on event 2 START Start counter on event 3 INC Increment counter on event 4 COUNT Count on active state of asynchronous event 5 STAMP Stamp capture 6 FAULT Non-recoverable fault 7 EVACT1 Timer/counter Input Event1 Action 3 3 EVACT1Select OFF Event action disabled 0 RETRIGGER Re-trigger counter on event 1 DIR Direction control 2 STOP Stop counter on event 3 DEC Decrement counter on event 4 PPW Period capture value in CC0 register, pulse width capture value in CC1 register 5 PWP Period capture value in CC1 register, pulse width capture value in CC0 register 6 FAULT Non-recoverable fault 7 MCEI0 Match or Capture Channel 0 Event Input Enable 16 1 MCEI1 Match or Capture Channel 1 Event Input Enable 17 1 MCEI2 Match or Capture Channel 2 Event Input Enable 18 1 MCEI3 Match or Capture Channel 3 Event Input Enable 19 1 MCEI4 Match or Capture Channel 4 Event Input Enable 20 1 MCEI5 Match or Capture Channel 5 Event Input Enable 21 1 MCEO0 Match or Capture Channel 0 Event Output Enable 24 1 MCEO1 Match or Capture Channel 1 Event Output Enable 25 1 MCEO2 Match or Capture Channel 2 Event Output Enable 26 1 MCEO3 Match or Capture Channel 3 Event Output Enable 27 1 MCEO4 Match or Capture Channel 4 Event Output Enable 28 1 MCEO5 Match or Capture Channel 5 Event Output Enable 29 1 OVFEO Overflow/Underflow Output Event Enable 8 1 TCEI0 Timer/counter Event 0 Input Enable 14 1 TCEI1 Timer/counter Event 1 Input Enable 15 1 TCINV0 Inverted Event 0 Input Enable 12 1 TCINV1 Inverted Event 1 Input Enable 13 1 TRGEO Retrigger Output Event Enable 9 1 TCC_FCTRLA Recoverable Fault A Configuration 0xC 32 read-write n 0x0 0x0 BLANK Fault A Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault A Blanking Prescaler 15 1 BLANKVAL Fault A Blanking Time 16 8 CAPTURE Fault A Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault A Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault A Filter Value 24 4 HALT Fault A Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault A Keeper 3 1 QUAL Fault A Qualification 4 1 RESTART Fault A Restart 7 1 SRC Fault A Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_FCTRLB Recoverable Fault B Configuration 0x10 32 read-write n 0x0 0x0 BLANK Fault B Blanking Mode 5 2 BLANKSelect START Blanking applied from start of the ramp 0 RISE Blanking applied from rising edge of the output waveform 1 FALL Blanking applied from falling edge of the output waveform 2 BOTH Blanking applied from each toggle of the output waveform 3 BLANKPRESC Fault B Blanking Prescaler 15 1 BLANKVAL Fault B Blanking Time 16 8 CAPTURE Fault B Capture Action 12 3 CAPTURESelect DISABLE No capture 0 CAPT Capture on fault 1 CAPTMIN Minimum capture 2 CAPTMAX Maximum capture 3 LOCMIN Minimum local detection 4 LOCMAX Maximum local detection 5 DERIV0 Minimum and maximum local detection 6 CAPTMARK Capture with ramp index as MSB value 7 CHSEL Fault B Capture Channel 10 2 CHSELSelect CC0 Capture value stored in channel 0 0 CC1 Capture value stored in channel 1 1 CC2 Capture value stored in channel 2 2 CC3 Capture value stored in channel 3 3 FILTERVAL Fault B Filter Value 24 4 HALT Fault B Halt Mode 8 2 HALTSelect DISABLE Halt action disabled 0 HW Hardware halt action 1 SW Software halt action 2 NR Non-recoverable fault 3 KEEP Fault B Keeper 3 1 QUAL Fault B Qualification 4 1 RESTART Fault B Restart 7 1 SRC Fault B Source 0 2 SRCSelect DISABLE Fault input disabled 0 ENABLE MCEx (x=0,1) event input 1 INVERT Inverted MCEx (x=0,1) event input 2 ALTFAULT Alternate fault (A or B) state at the end of the previous period 3 TCC_INTENCLR Interrupt Enable Clear 0x24 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTENSET Interrupt Enable Set 0x28 32 read-write n 0x0 0x0 CNT Counter Interrupt Enable 2 1 DFS Non-Recoverable Debug Fault Interrupt Enable 11 1 ERR Error Interrupt Enable 3 1 FAULT0 Non-Recoverable Fault 0 Interrupt Enable 14 1 FAULT1 Non-Recoverable Fault 1 Interrupt Enable 15 1 FAULTA Recoverable Fault A Interrupt Enable 12 1 FAULTB Recoverable Fault B Interrupt Enable 13 1 MC0 Match or Capture Channel 0 Interrupt Enable 16 1 MC1 Match or Capture Channel 1 Interrupt Enable 17 1 MC2 Match or Capture Channel 2 Interrupt Enable 18 1 MC3 Match or Capture Channel 3 Interrupt Enable 19 1 MC4 Match or Capture Channel 4 Interrupt Enable 20 1 MC5 Match or Capture Channel 5 Interrupt Enable 21 1 OVF Overflow Interrupt Enable 0 1 TRG Retrigger Interrupt Enable 1 1 UFS Non-Recoverable Update Fault Interrupt Enable 10 1 TCC_INTFLAG Interrupt Flag Status and Clear 0x2C 32 read-write n 0x0 0x0 CNT Counter 2 1 DFS Non-Recoverable Debug Fault 11 1 ERR Error 3 1 FAULT0 Non-Recoverable Fault 0 14 1 FAULT1 Non-Recoverable Fault 1 15 1 FAULTA Recoverable Fault A 12 1 FAULTB Recoverable Fault B 13 1 MC0 Match or Capture 0 16 1 MC1 Match or Capture 1 17 1 MC2 Match or Capture 2 18 1 MC3 Match or Capture 3 19 1 MC4 Match or Capture 4 20 1 MC5 Match or Capture 5 21 1 OVF Overflow 0 1 TRG Retrigger 1 1 UFS Non-Recoverable Update Fault 10 1 TCC_PATT Pattern 0x38 16 read-write n 0x0 0x0 PGE0 Pattern Generator 0 Output Enable 0 1 PGE1 Pattern Generator 1 Output Enable 1 1 PGE2 Pattern Generator 2 Output Enable 2 1 PGE3 Pattern Generator 3 Output Enable 3 1 PGE4 Pattern Generator 4 Output Enable 4 1 PGE5 Pattern Generator 5 Output Enable 5 1 PGE6 Pattern Generator 6 Output Enable 6 1 PGE7 Pattern Generator 7 Output Enable 7 1 PGV0 Pattern Generator 0 Output Value 8 1 PGV1 Pattern Generator 1 Output Value 9 1 PGV2 Pattern Generator 2 Output Value 10 1 PGV3 Pattern Generator 3 Output Value 11 1 PGV4 Pattern Generator 4 Output Value 12 1 PGV5 Pattern Generator 5 Output Value 13 1 PGV6 Pattern Generator 6 Output Value 14 1 PGV7 Pattern Generator 7 Output Value 15 1 TCC_PATTBUF Pattern Buffer 0x64 16 read-write n 0x0 0x0 PGEB0 Pattern Generator 0 Output Enable Buffer 0 1 PGEB1 Pattern Generator 1 Output Enable Buffer 1 1 PGEB2 Pattern Generator 2 Output Enable Buffer 2 1 PGEB3 Pattern Generator 3 Output Enable Buffer 3 1 PGEB4 Pattern Generator 4 Output Enable Buffer 4 1 PGEB5 Pattern Generator 5 Output Enable Buffer 5 1 PGEB6 Pattern Generator 6 Output Enable Buffer 6 1 PGEB7 Pattern Generator 7 Output Enable Buffer 7 1 PGVB0 Pattern Generator 0 Output Enable 8 1 PGVB1 Pattern Generator 1 Output Enable 9 1 PGVB2 Pattern Generator 2 Output Enable 10 1 PGVB3 Pattern Generator 3 Output Enable 11 1 PGVB4 Pattern Generator 4 Output Enable 12 1 PGVB5 Pattern Generator 5 Output Enable 13 1 PGVB6 Pattern Generator 6 Output Enable 14 1 PGVB7 Pattern Generator 7 Output Enable 15 1 TCC_PER Period 0x40 32 read-write n 0x0 0x0 PER Period Value 0 24 TCC_PERBUF Period Buffer 0x6C 32 read-write n 0x0 0x0 PERBUF Period Buffer Value 0 24 TCC_PERBUF_DITH4_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 4 PERBUF Period Buffer Value 4 20 TCC_PERBUF_DITH5_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 5 PERBUF Period Buffer Value 5 19 TCC_PERBUF_DITH6_MODE Period Buffer PERBUF 0x6C 32 read-write n 0x0 0x0 DITHERBUF Dithering Buffer Cycle Number 0 6 PERBUF Period Buffer Value 6 18 TCC_PER_DITH4_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 4 PER Period Value 4 20 TCC_PER_DITH5_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 5 PER Period Value 5 19 TCC_PER_DITH6_MODE Period PER 0x40 32 read-write n 0x0 0x0 DITHER Dithering Cycle Number 0 6 PER Period Value 6 18 TCC_STATUS Status 0x30 32 read-write n 0x0 0x0 CCBUFV0 Compare Channel 0 Buffer Valid 16 1 CCBUFV1 Compare Channel 1 Buffer Valid 17 1 CCBUFV2 Compare Channel 2 Buffer Valid 18 1 CCBUFV3 Compare Channel 3 Buffer Valid 19 1 CCBUFV4 Compare Channel 4 Buffer Valid 20 1 CCBUFV5 Compare Channel 5 Buffer Valid 21 1 CMP0 Compare Channel 0 Value 24 1 CMP1 Compare Channel 1 Value 25 1 CMP2 Compare Channel 2 Value 26 1 CMP3 Compare Channel 3 Value 27 1 CMP4 Compare Channel 4 Value 28 1 CMP5 Compare Channel 5 Value 29 1 DFS Non-Recoverable Debug Fault State 3 1 FAULT0 Non-Recoverable Fault 0 State 14 1 FAULT0IN Non-Recoverable Fault0 Input 10 1 FAULT1 Non-Recoverable Fault 1 State 15 1 FAULT1IN Non-Recoverable Fault1 Input 11 1 FAULTA Recoverable Fault A State 12 1 FAULTAIN Recoverable Fault A Input 8 1 FAULTB Recoverable Fault B State 13 1 FAULTBIN Recoverable Fault B Input 9 1 IDX Ramp 1 1 PATTBUFV Pattern Buffer Valid 5 1 PERBUFV Period Buffer Valid 7 1 SLAVE Slave 4 1 STOP Stop 0 1 UFS Non-recoverable Update Fault State 2 1 TCC_SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 CC0 Compare Channel 0 Busy 8 1 CC1 Compare Channel 1 Busy 9 1 CC2 Compare Channel 2 Busy 10 1 CC3 Compare Channel 3 Busy 11 1 CC4 Compare Channel 4 Busy 12 1 CC5 Compare Channel 5 Busy 13 1 COUNT Count Busy 4 1 CTRLB Ctrlb Busy 2 1 ENABLE Enable Busy 1 1 PATT Pattern Busy 5 1 PER Period Busy 7 1 STATUS Status Busy 3 1 SWRST Swrst Busy 0 1 WAVE Wave Busy 6 1 TCC_WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 TCC_WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 WAVE Waveform Control 0x3C 32 read-write n 0x0 0x0 CICCEN0 Circular Channel 0 Enable 8 1 CICCEN1 Circular Channel 1 Enable 9 1 CICCEN2 Circular Channel 2 Enable 10 1 CICCEN3 Circular Channel 3 Enable 11 1 CIPEREN Circular period Enable 7 1 POL0 Channel 0 Polarity 16 1 POL1 Channel 1 Polarity 17 1 POL2 Channel 2 Polarity 18 1 POL3 Channel 3 Polarity 19 1 POL4 Channel 4 Polarity 20 1 POL5 Channel 5 Polarity 21 1 RAMP Ramp Mode 4 2 RAMPSelect RAMP1 RAMP1 operation 0 RAMP2A Alternative RAMP2 operation 1 RAMP2 RAMP2 operation 2 RAMP2C Critical RAMP2 operation 3 SWAP0 Swap DTI Output Pair 0 24 1 SWAP1 Swap DTI Output Pair 1 25 1 SWAP2 Swap DTI Output Pair 2 26 1 SWAP3 Swap DTI Output Pair 3 27 1 WAVEGEN Waveform Generation 0 3 WAVEGENSelect NFRQ Normal frequency 0 MFRQ Match frequency 1 NPWM Normal PWM 2 DSCRITICAL Dual-slope critical 4 DSBOTTOM Dual-slope with interrupt/event condition when COUNT reaches ZERO 5 DSBOTH Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP 6 DSTOP Dual-slope with interrupt/event condition when COUNT reaches TOP 7 WEXCTRL Waveform Extension Configuration 0x14 32 read-write n 0x0 0x0 DTHS Dead-time High Side Outputs Value 24 8 DTIEN0 Dead-time Insertion Generator 0 Enable 8 1 DTIEN1 Dead-time Insertion Generator 1 Enable 9 1 DTIEN2 Dead-time Insertion Generator 2 Enable 10 1 DTIEN3 Dead-time Insertion Generator 3 Enable 11 1 DTLS Dead-time Low Side Outputs Value 16 8 OTMX Output Matrix 0 2 TPI Trace Port Interface Register TPI 0x0 0x0 0xFD0 registers n ACPR Asynchronous Clock Prescaler Register 0x10 32 read-write n 0x0 0x0 PRESCALER 0 13 CLAIMCLR Claim tag clear 0xFA4 32 read-write n 0x0 0x0 CLAIMSET Claim tag set 0xFA0 32 read-write n 0x0 0x0 CSPSR Current Parallel Port Size Register 0x4 32 read-write n 0x0 0x0 DEVID TPIU_DEVID 0xFC8 32 read-only n 0x0 0x0 AsynClkIn 5 1 MANCVALID 10 1 MinBufSz 6 3 NrTraceInput 0 1 NRZVALID 11 1 PTINVALID 9 1 DEVTYPE TPIU_DEVTYPE 0xFCC 32 read-only n 0x0 0x0 MajorType 4 4 SubType 0 4 FFCR Formatter and Flush Control Register 0x304 32 read-write n 0x0 0x0 EnFCont 1 1 TrigIn 8 1 FFSR Formatter and Flush Status Register 0x300 32 read-only n 0x0 0x0 FlInProg 0 1 FtNonStop 3 1 FtStopped 1 1 TCPresent 2 1 FIFO0 Integration ETM Data 0xEEC 32 read-only n 0x0 0x0 ETM0 0 8 ETM1 8 8 ETM2 16 8 ETM_ATVALID 26 1 ETM_bytecount 24 2 ITM_ATVALID 29 1 ITM_bytecount 27 2 FIFO1 Integration ITM Data 0xEFC 32 read-only n 0x0 0x0 ETM_ATVALID 26 1 ETM_bytecount 24 2 ITM0 0 8 ITM1 8 8 ITM2 16 8 ITM_ATVALID 29 1 ITM_bytecount 27 2 FSCR Formatter Synchronization Counter Register 0x308 32 read-only n 0x0 0x0 ITATBCTR0 ITATBCTR0 0xEF8 32 read-only n 0x0 0x0 ATREADY 0 1 ITATBCTR2 ITATBCTR2 0xEF0 32 read-only n 0x0 0x0 ATREADY 0 1 ITCTRL Integration Mode Control 0xF00 32 read-write n 0x0 0x0 Mode 0 1 SPPR Selected Pin Protocol Register 0xF0 32 read-write n 0x0 0x0 TXMODE 0 2 SSPSR Supported Parallel Port Size Register 0x0 32 read-only n 0x0 0x0 TRIGGER TRIGGER 0xEE8 32 read-only n 0x0 0x0 TRIGGER 0 1 TPIU Trace Port Interface Unit TPIU 0x0 0x0 0xFD0 registers n ACPR Asynchronous Clock Prescaler Register 0x10 32 read-write n 0x0 0x0 PRESCALER 0 13 CLAIMCLR Claim tag clear 0xFA4 32 read-write n 0x0 0x0 CLAIMSET Claim tag set 0xFA0 32 read-write n 0x0 0x0 CSPSR Current Parallel Port Size Register 0x4 32 read-write n 0x0 0x0 DEVID TPIU_DEVID 0xFC8 32 read-only n 0x0 0x0 AsynClkIn 5 1 MANCVALID 10 1 MinBufSz 6 3 NrTraceInput 0 1 NRZVALID 11 1 PTINVALID 9 1 DEVTYPE TPIU_DEVTYPE 0xFCC 32 read-only n 0x0 0x0 MajorType 4 4 SubType 0 4 FFCR Formatter and Flush Control Register 0x304 32 read-write n 0x0 0x0 EnFCont 1 1 TrigIn 8 1 FFSR Formatter and Flush Status Register 0x300 32 read-only n 0x0 0x0 FlInProg 0 1 FtNonStop 3 1 FtStopped 1 1 TCPresent 2 1 FIFO0 Integration ETM Data 0xEEC 32 read-only n 0x0 0x0 ETM0 0 8 ETM1 8 8 ETM2 16 8 ETM_ATVALID 26 1 ETM_bytecount 24 2 ITM_ATVALID 29 1 ITM_bytecount 27 2 FIFO1 Integration ITM Data 0xEFC 32 read-only n 0x0 0x0 ETM_ATVALID 26 1 ETM_bytecount 24 2 ITM0 0 8 ITM1 8 8 ITM2 16 8 ITM_ATVALID 29 1 ITM_bytecount 27 2 FSCR Formatter Synchronization Counter Register 0x308 32 read-only n 0x0 0x0 ITATBCTR0 ITATBCTR0 0xEF8 32 read-only n 0x0 0x0 ATREADY 0 1 ITATBCTR2 ITATBCTR2 0xEF0 32 read-only n 0x0 0x0 ATREADY 0 1 ITCTRL Integration Mode Control 0xF00 32 read-write n 0x0 0x0 Mode 0 1 SPPR Selected Pin Protocol Register 0xF0 32 read-write n 0x0 0x0 TXMODE 0 2 SSPSR Supported Parallel Port Size Register 0x0 32 read-only n 0x0 0x0 TRIGGER TRIGGER 0xEE8 32 read-only n 0x0 0x0 TRIGGER 0 1 TRNG True Random Generator TRNG 0x0 0x0 0x24 registers n TRNG 131 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 RUNSTDBY Run in Standby 6 1 DATA Output Data 0x20 32 read-only n 0x0 0x0 DATA Output Data 0 32 EVCTRL Event Control 0x4 8 read-write n 0x0 0x0 DATARDYEO Data Ready Event Output 0 1 INTENCLR Interrupt Enable Clear 0x8 8 read-write n 0x0 0x0 DATARDY Data Ready Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x9 8 read-write n 0x0 0x0 DATARDY Data Ready Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0xA 8 read-write n 0x0 0x0 DATARDY Data Ready Interrupt Flag 0 1 USB Universal Serial Bus USB 0x0 0x0 0x200 registers n USB_OTHER 80 USB_SOF_HSOF 81 USB_TRCPT0 82 USB_TRCPT1 83 BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 CTRLA Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0 HOST Host Mode 1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 CTRLB HOST Control B 0x8 16 read-write n 0x0 0x0 AUTORESUME Auto Resume Enable 4 1 BUSRESET Send USB Reset 9 1 DETACH Detach 0 1 GNAK Global NAK 9 1 L1RESUME Send L1 Resume 11 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0 ACK ACK 1 NYET NYET 2 STALL STALL 3 NREPLY No Reply 4 1 OPMODE2 Specific Operational Mode 8 1 RESUME Send USB Resume 1 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0x0 LS LS : Low Speed 0x1 HS HS : High Speed capable 0x2 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 0x3 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 0x3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 UPRSM Upstream Resume 1 1 VBUSOK VBUS is OK 10 1 DADD DEVICE Device Address 0xA 8 read-write n 0x0 0x0 ADDEN Device Address Enable 7 1 DADD Device Address 0 7 DESCADD Descriptor Address 0x24 32 read-write n 0x0 0x0 DESCADD Descriptor Address Value 0 32 DEVICE - CTRLA USB is Device - - Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0 HOST Host Mode 1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 DEVICE - CTRLB USB is Device - - DEVICE Control B 0x8 16 read-write n 0x0 0x0 DETACH Detach 0 1 GNAK Global NAK 9 1 LPMHDSK Link Power Management Handshake 10 2 LPMHDSKSelect NO No handshake. LPM is not supported 0 ACK ACK 1 NYET NYET 2 STALL STALL 3 NREPLY No Reply 4 1 OPMODE2 Specific Operational Mode 8 1 SPDCONF Speed Configuration 2 2 SPDCONFSelect FS FS : Full Speed 0 LS LS : Low Speed 1 HS HS : High Speed capable 2 HSTM HSTM: High Speed Test Mode (force high-speed mode for test mode) 3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 TSTPCKT Test packet mode 7 1 UPRSM Upstream Resume 1 1 DEVICE - DADD USB is Device - - DEVICE Device Address 0xA 8 read-write n 0x0 0x0 ADDEN Device Address Enable 7 1 DADD Device Address 0 7 DEVICE - DESCADD USB is Device - - Descriptor Address 0x24 32 read-write n 0x0 0x0 DESCADD Descriptor Address Value 0 32 DEVICE - EPINTSMRY USB is Device - - DEVICE End Point Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 End Point 0 Interrupt 0 1 EPINT1 End Point 1 Interrupt 1 1 EPINT2 End Point 2 Interrupt 2 1 EPINT3 End Point 3 Interrupt 3 1 EPINT4 End Point 4 Interrupt 4 1 EPINT5 End Point 5 Interrupt 5 1 EPINT6 End Point 6 Interrupt 6 1 EPINT7 End Point 7 Interrupt 7 1 DEVICE - FNUM USB is Device - - DEVICE Device Frame Number 0x10 16 read-only n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 DEVICE - FSMSTATUS USB is Device - - Finite State Machine Status 0xD 8 read-only n 0x0 0x0 FSMSTATE Fine State Machine Status 0 7 FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 1 DNRESUME DNRESUME. Down Stream Resume. 16 ON ON (L0). It corresponds to the Idle and Active states 2 UPRESUME UPRESUME. Up Stream Resume. 32 SUSPEND SUSPEND (L2) 4 RESET RESET. USB lines Reset. 64 SLEEP SLEEP (L1) 8 DEVICE - INTENCLR USB is Device - - DEVICE Device Interrupt Enable Clear 0x14 16 read-write n 0x0 0x0 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 DEVICE - INTENSET USB is Device - - DEVICE Device Interrupt Enable Set 0x18 16 read-write n 0x0 0x0 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 DEVICE - INTFLAG USB is Device - - DEVICE Device Interrupt Flag 0x1C 16 read-write n 0x0 0x0 EORSM End Of Resume 5 1 EORST End of Reset 3 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 MSOF Micro Start of Frame in High Speed Mode 1 1 RAMACER Ram Access 7 1 SOF Start Of Frame 2 1 SUSPEND Suspend 0 1 UPRSM Upstream Resume 6 1 WAKEUP Wake Up 4 1 DEVICE - PADCAL USB is Device - - USB PAD Calibration 0x28 16 read-write n 0x0 0x0 TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 DEVICE - QOSCTRL USB is Device - - USB Quality Of Service 0x3 8 read-write n 0x0 0x0 CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 DEVICE - STATUS USB is Device - - DEVICE Status 0xC 8 read-only n 0x0 0x0 LINESTATE USB Line State Status 6 2 LINESTATESelect 0 SE0/RESET 0 1 FS-J or LS-K State 1 2 FS-K or LS-J State 2 SPEED Speed Status 2 2 SPEEDSelect FS Full-speed mode 0 LS Low-speed mode 1 HS High-speed mode 2 DEVICE - SYNCBUSY USB is Device - - Synchronization Busy 0x2 8 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy 1 1 SWRST Software Reset Synchronization Busy 0 1 DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x100 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x108 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x109 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x107 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x106 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x104 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x105 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x220 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x228 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x229 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x227 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x226 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x224 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x225 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x360 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x368 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x369 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x367 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x366 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x364 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x365 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x4C0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x4C8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x4C9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x4C7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x4C6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x4C4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x4C5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x640 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x648 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x649 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x647 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x646 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x644 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x645 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x7E0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x7E8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x7E9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x7E7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x7E6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x7E4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x7E5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0x9A0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x9A8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x9A9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x9A7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x9A6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x9A4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x9A5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPCFG DEVICE_ENDPOINT End Point Configuration 0xB80 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0xB88 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0xB89 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0xB87 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0xB86 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0xB84 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 DEVICE_ENDPOINT[7]-DEVICE_ENDPOINT[6]-DEVICE_ENDPOINT[5]-DEVICE_ENDPOINT[4]-DEVICE_ENDPOINT[3]-DEVICE_ENDPOINT[2]-DEVICE_ENDPOINT[1]-DEVICE_ENDPOINT[0]-EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0xB85 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 EPCFG DEVICE_ENDPOINT End Point Configuration 0x0 8 read-write n 0x0 0x0 EPTYPE0 End Point Type0 0 3 EPTYPE1 End Point Type1 4 3 NYETDIS NYET Token Disable 7 1 EPINTENCLR DEVICE_ENDPOINT End Point Interrupt Clear Flag 0x8 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Disable 4 1 STALL0 Stall 0 In/Out Interrupt Disable 5 1 STALL1 Stall 1 In/Out Interrupt Disable 6 1 TRCPT0 Transfer Complete 0 Interrupt Disable 0 1 TRCPT1 Transfer Complete 1 Interrupt Disable 1 1 TRFAIL0 Error Flow 0 Interrupt Disable 2 1 TRFAIL1 Error Flow 1 Interrupt Disable 3 1 EPINTENSET DEVICE_ENDPOINT End Point Interrupt Set Flag 0x9 8 read-write n 0x0 0x0 RXSTP Received Setup Interrupt Enable 4 1 STALL0 Stall 0 In/out Interrupt enable 5 1 STALL1 Stall 1 In/out Interrupt enable 6 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL0 Error Flow 0 Interrupt Enable 2 1 TRFAIL1 Error Flow 1 Interrupt Enable 3 1 EPINTFLAG DEVICE_ENDPOINT End Point Interrupt Flag 0x7 8 read-write n 0x0 0x0 RXSTP Received Setup 4 1 STALL0 Stall 0 In/out 5 1 STALL1 Stall 1 In/out 6 1 TRCPT0 Transfer Complete 0 0 1 TRCPT1 Transfer Complete 1 1 1 TRFAIL0 Error Flow 0 2 1 TRFAIL1 Error Flow 1 3 1 EPINTSMRY DEVICE End Point Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 End Point 0 Interrupt 0 1 EPINT1 End Point 1 Interrupt 1 1 EPINT2 End Point 2 Interrupt 2 1 EPINT3 End Point 3 Interrupt 3 1 EPINT4 End Point 4 Interrupt 4 1 EPINT5 End Point 5 Interrupt 5 1 EPINT6 End Point 6 Interrupt 6 1 EPINT7 End Point 7 Interrupt 7 1 EPSTATUS DEVICE_ENDPOINT End Point Pipe Status 0x6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGLIN Data Toggle In 1 1 DTGLOUT Data Toggle Out 0 1 STALLRQ0 Stall 0 Request 4 1 STALLRQ1 Stall 1 Request 5 1 EPSTATUSCLR DEVICE_ENDPOINT End Point Pipe Status Clear 0x4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Current Bank Clear 2 1 DTGLIN Data Toggle IN Clear 1 1 DTGLOUT Data Toggle OUT Clear 0 1 STALLRQ0 Stall 0 Request Clear 4 1 STALLRQ1 Stall 1 Request Clear 5 1 EPSTATUSSET DEVICE_ENDPOINT End Point Pipe Status Set 0x5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGLIN Data Toggle IN Set 1 1 DTGLOUT Data Toggle OUT Set 0 1 STALLRQ0 Stall 0 Request Set 4 1 STALLRQ1 Stall 1 Request Set 5 1 FLENHIGH HOST Host Frame Length 0x12 8 read-only n 0x0 0x0 FLENHIGH Frame Length 0 8 FNUM HOST Host Frame Number 0x10 16 read-write n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 FSMSTATUS Finite State Machine Status 0xD 8 read-only n 0x0 0x0 FSMSTATE Fine State Machine Status 0 7 FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 0x1 DNRESUME DNRESUME. Down Stream Resume. 0x10 ON ON (L0). It corresponds to the Idle and Active states 0x2 UPRESUME UPRESUME. Up Stream Resume. 0x20 SUSPEND SUSPEND (L2) 0x4 RESET RESET. USB lines Reset. 0x40 SLEEP SLEEP (L1) 0x8 HOST - CTRLA USB is Host - - Control A 0x0 8 read-write n 0x0 0x0 ENABLE Enable 1 1 MODE Operating Mode 7 1 MODESelect DEVICE Device Mode 0 HOST Host Mode 1 RUNSTDBY Run in Standby Mode 2 1 SWRST Software Reset 0 1 HOST - CTRLB USB is Host - - HOST Control B 0x8 16 read-write n 0x0 0x0 AUTORESUME Auto Resume Enable 4 1 BUSRESET Send USB Reset 9 1 L1RESUME Send L1 Resume 11 1 RESUME Send USB Resume 1 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Speed Configuration for Host 2 2 SPDCONFSelect NORMAL Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. 0 FS Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. 3 TSTJ Test mode J 5 1 TSTK Test mode K 6 1 VBUSOK VBUS is OK 10 1 HOST - DESCADD USB is Host - - Descriptor Address 0x24 32 read-write n 0x0 0x0 DESCADD Descriptor Address Value 0 32 HOST - FLENHIGH USB is Host - - HOST Host Frame Length 0x12 8 read-only n 0x0 0x0 FLENHIGH Frame Length 0 8 HOST - FNUM USB is Host - - HOST Host Frame Number 0x10 16 read-write n 0x0 0x0 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 HOST - FSMSTATUS USB is Host - - Finite State Machine Status 0xD 8 read-only n 0x0 0x0 FSMSTATE Fine State Machine Status 0 7 FSMSTATESelect OFF OFF (L3). It corresponds to the powered-off, disconnected, and disabled state 1 DNRESUME DNRESUME. Down Stream Resume. 16 ON ON (L0). It corresponds to the Idle and Active states 2 UPRESUME UPRESUME. Up Stream Resume. 32 SUSPEND SUSPEND (L2) 4 RESET RESET. USB lines Reset. 64 SLEEP SLEEP (L1) 8 HOST - HSOFC USB is Host - - HOST Host Start Of Frame Control 0xA 8 read-write n 0x0 0x0 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 HOST - INTENCLR USB is Host - - HOST Host Interrupt Enable Clear 0x14 16 read-write n 0x0 0x0 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 DNRSM DownStream to Device Interrupt Disable 5 1 HSOF Host Start Of Frame Interrupt Disable 2 1 RAMACER Ram Access Interrupt Disable 7 1 RST BUS Reset Interrupt Disable 3 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 WAKEUP Wake Up Interrupt Disable 4 1 HOST - INTENSET USB is Host - - HOST Host Interrupt Enable Set 0x18 16 read-write n 0x0 0x0 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 DNRSM DownStream to the Device Interrupt Enable 5 1 HSOF Host Start Of Frame Interrupt Enable 2 1 RAMACER Ram Access Interrupt Enable 7 1 RST Bus Reset Interrupt Enable 3 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 HOST - INTFLAG USB is Host - - HOST Host Interrupt Flag 0x1C 16 read-write n 0x0 0x0 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 DNRSM Downstream 5 1 HSOF Host Start Of Frame 2 1 RAMACER Ram Access 7 1 RST Bus Reset 3 1 UPRSM Upstream Resume from the Device 6 1 WAKEUP Wake Up 4 1 HOST - PADCAL USB is Host - - USB PAD Calibration 0x28 16 read-write n 0x0 0x0 TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 HOST - PINTSMRY USB is Host - - HOST Pipe Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 Pipe 0 Interrupt 0 1 EPINT1 Pipe 1 Interrupt 1 1 EPINT2 Pipe 2 Interrupt 2 1 EPINT3 Pipe 3 Interrupt 3 1 EPINT4 Pipe 4 Interrupt 4 1 EPINT5 Pipe 5 Interrupt 5 1 EPINT6 Pipe 6 Interrupt 6 1 EPINT7 Pipe 7 Interrupt 7 1 HOST - QOSCTRL USB is Host - - USB Quality Of Service 0x3 8 read-write n 0x0 0x0 CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 HOST - STATUS USB is Host - - HOST Status 0xC 8 read-write n 0x0 0x0 LINESTATE USB Line State Status 6 2 SPEED Speed Status 2 2 HOST - SYNCBUSY USB is Host - - Synchronization Busy 0x2 8 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy 1 1 SWRST Software Reset Synchronization Busy 0 1 HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x103 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x100 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x108 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x109 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x107 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x106 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x104 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x105 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x223 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x220 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x228 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x229 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x227 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x226 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x224 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x225 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x363 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x360 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x368 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x369 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x367 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x366 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x364 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x365 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x4C3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x4C0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x4C8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x4C9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x4C7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x4C6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x4C4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x4C5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x643 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x640 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x648 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x649 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x647 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x646 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x644 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x645 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x7E3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x7E0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x7E8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x7E9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x7E7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x7E6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x7E4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x7E5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0x9A3 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0x9A0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x9A8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x9A9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x9A7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0x9A6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x9A4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x9A5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-BINTERVAL HOST_PIPE Bus Access Period of Pipe 0xB83 8 read-write n 0x0 0x0 BITINTERVAL Bit Interval 0 8 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PCFG HOST_PIPE End Point Configuration 0xB80 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0xB88 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0xB89 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PINTFLAG HOST_PIPE Pipe Interrupt Flag 0xB87 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUS HOST_PIPE End Point Pipe Status 0xB86 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0xB84 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 HOST_PIPE[7]-HOST_PIPE[6]-HOST_PIPE[5]-HOST_PIPE[4]-HOST_PIPE[3]-HOST_PIPE[2]-HOST_PIPE[1]-HOST_PIPE[0]-PSTATUSSET HOST_PIPE End Point Pipe Status Set 0xB85 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 HSOFC HOST Host Start Of Frame Control 0xA 8 read-write n 0x0 0x0 FLENC Frame Length Control 0 4 FLENCE Frame Length Control Enable 7 1 INTENCLR HOST Host Interrupt Enable Clear 0x14 16 read-write n 0x0 0x0 DCONN Device Connection Interrupt Disable 8 1 DDISC Device Disconnection Interrupt Disable 9 1 DNRSM DownStream to Device Interrupt Disable 5 1 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 HSOF Host Start Of Frame Interrupt Disable 2 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Disable 7 1 RST BUS Reset Interrupt Disable 3 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume from Device Interrupt Disable 6 1 WAKEUP Wake Up Interrupt Disable 4 1 INTENSET HOST Host Interrupt Enable Set 0x18 16 read-write n 0x0 0x0 DCONN Link Power Management Interrupt Enable 8 1 DDISC Device Disconnection Interrupt Enable 9 1 DNRSM DownStream to the Device Interrupt Enable 5 1 EORSM End Of Resume Interrupt Enable 5 1 EORST End of Reset Interrupt Enable 3 1 HSOF Host Start Of Frame Interrupt Enable 2 1 LPMNYET Link Power Management Not Yet Interrupt Enable 8 1 LPMSUSP Link Power Management Suspend Interrupt Enable 9 1 MSOF Micro Start of Frame Interrupt Enable in High Speed Mode 1 1 RAMACER Ram Access Interrupt Enable 7 1 RST Bus Reset Interrupt Enable 3 1 SOF Start Of Frame Interrupt Enable 2 1 SUSPEND Suspend Interrupt Enable 0 1 UPRSM Upstream Resume fromthe device Interrupt Enable 6 1 WAKEUP Wake Up Interrupt Enable 4 1 INTFLAG HOST Host Interrupt Flag 0x1C 16 read-write n 0x0 0x0 DCONN Device Connection 8 1 DDISC Device Disconnection 9 1 DNRSM Downstream 5 1 EORSM End Of Resume 5 1 EORST End of Reset 3 1 HSOF Host Start Of Frame 2 1 LPMNYET Link Power Management Not Yet 8 1 LPMSUSP Link Power Management Suspend 9 1 MSOF Micro Start of Frame in High Speed Mode 1 1 RAMACER Ram Access 7 1 RST Bus Reset 3 1 SOF Start Of Frame 2 1 SUSPEND Suspend 0 1 UPRSM Upstream Resume from the Device 6 1 WAKEUP Wake Up 4 1 PADCAL USB PAD Calibration 0x28 16 read-write n 0x0 0x0 TRANSN USB Pad Transn calibration 6 5 TRANSP USB Pad Transp calibration 0 5 TRIM USB Pad Trim calibration 12 3 PCFG HOST_PIPE End Point Configuration 0x0 8 read-write n 0x0 0x0 BK Pipe Bank 2 1 PTOKEN Pipe Token 0 2 PTYPE Pipe Type 3 3 PINTENCLR HOST_PIPE Pipe Interrupt Flag Clear 0x8 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Disable 3 1 STALL Stall Inetrrupt Disable 5 1 TRCPT0 Transfer Complete 0 Disable 0 1 TRCPT1 Transfer Complete 1 Disable 1 1 TRFAIL Error Flow Interrupt Disable 2 1 TXSTP Transmit Setup Interrupt Disable 4 1 PINTENSET HOST_PIPE Pipe Interrupt Flag Set 0x9 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Enable 3 1 STALL Stall Interrupt Enable 5 1 TRCPT0 Transfer Complete 0 Interrupt Enable 0 1 TRCPT1 Transfer Complete 1 Interrupt Enable 1 1 TRFAIL Error Flow Interrupt Enable 2 1 TXSTP Transmit Setup Interrupt Enable 4 1 PINTFLAG HOST_PIPE Pipe Interrupt Flag 0x7 8 read-write n 0x0 0x0 PERR Pipe Error Interrupt Flag 3 1 STALL Stall Interrupt Flag 5 1 TRCPT0 Transfer Complete 0 Interrupt Flag 0 1 TRCPT1 Transfer Complete 1 Interrupt Flag 1 1 TRFAIL Error Flow Interrupt Flag 2 1 TXSTP Transmit Setup Interrupt Flag 4 1 PINTSMRY HOST Pipe Interrupt Summary 0x20 16 read-only n 0x0 0x0 EPINT0 Pipe 0 Interrupt 0 1 EPINT1 Pipe 1 Interrupt 1 1 EPINT2 Pipe 2 Interrupt 2 1 EPINT3 Pipe 3 Interrupt 3 1 EPINT4 Pipe 4 Interrupt 4 1 EPINT5 Pipe 5 Interrupt 5 1 EPINT6 Pipe 6 Interrupt 6 1 EPINT7 Pipe 7 Interrupt 7 1 PSTATUS HOST_PIPE End Point Pipe Status 0x6 8 read-only n 0x0 0x0 BK0RDY Bank 0 ready 6 1 BK1RDY Bank 1 ready 7 1 CURBK Current Bank 2 1 DTGL Data Toggle 0 1 PFREEZE Pipe Freeze 4 1 PSTATUSCLR HOST_PIPE End Point Pipe Status Clear 0x4 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Clear 6 1 BK1RDY Bank 1 Ready Clear 7 1 CURBK Curren Bank clear 2 1 DTGL Data Toggle clear 0 1 PFREEZE Pipe Freeze Clear 4 1 PSTATUSSET HOST_PIPE End Point Pipe Status Set 0x5 8 write-only n 0x0 0x0 BK0RDY Bank 0 Ready Set 6 1 BK1RDY Bank 1 Ready Set 7 1 CURBK Current Bank Set 2 1 DTGL Data Toggle Set 0 1 PFREEZE Pipe Freeze Set 4 1 QOSCTRL USB Quality Of Service 0x3 8 read-write n 0x0 0x0 CQOS Configuration Quality of Service 0 2 DQOS Data Quality of Service 2 2 STATUS HOST Status 0xC 8 read-write n 0x0 0x0 LINESTATE USB Line State Status 6 2 LINESTATESelect 0 SE0/RESET 0x0 1 FS-J or LS-K State 0x1 2 FS-K or LS-J State 0x2 SPEED Speed Status 2 2 SPEEDSelect FS Full-speed mode 0x0 LS Low-speed mode 0x1 HS High-speed mode 0x2 SYNCBUSY Synchronization Busy 0x2 8 read-only n 0x0 0x0 ENABLE Enable Synchronization Busy 1 1 SWRST Software Reset Synchronization Busy 0 1 WDT Watchdog Timer WDT 0x0 0x0 0xD registers n WDT 10 CLEAR Clear 0xC 8 write-only n 0x0 0x0 CLEAR Watchdog Clear 0 8 CLEARSelect KEY Clear Key 165 CONFIG Configuration 0x1 8 read-write n 0x0 0x0 PER Time-Out Period 0 4 PERSelect CYC8 8 clock cycles 0 CYC16 16 clock cycles 1 CYC8192 8192 clock cycles 10 CYC16384 16384 clock cycles 11 CYC32 32 clock cycles 2 CYC64 64 clock cycles 3 CYC128 128 clock cycles 4 CYC256 256 clock cycles 5 CYC512 512 clock cycles 6 CYC1024 1024 clock cycles 7 CYC2048 2048 clock cycles 8 CYC4096 4096 clock cycles 9 WINDOW Window Mode Time-Out Period 4 4 WINDOWSelect CYC8 8 clock cycles 0 CYC16 16 clock cycles 1 CYC8192 8192 clock cycles 10 CYC16384 16384 clock cycles 11 CYC32 32 clock cycles 2 CYC64 64 clock cycles 3 CYC128 128 clock cycles 4 CYC256 256 clock cycles 5 CYC512 512 clock cycles 6 CYC1024 1024 clock cycles 7 CYC2048 2048 clock cycles 8 CYC4096 4096 clock cycles 9 CTRLA Control 0x0 8 read-write n 0x0 0x0 ALWAYSON Always-On 7 1 ENABLE Enable 1 1 WEN Watchdog Timer Window Mode Enable 2 1 EWCTRL Early Warning Interrupt Control 0x2 8 read-write n 0x0 0x0 EWOFFSET Early Warning Interrupt Time Offset 0 4 EWOFFSETSelect CYC8 8 clock cycles 0 CYC16 16 clock cycles 1 CYC8192 8192 clock cycles 10 CYC16384 16384 clock cycles 11 CYC32 32 clock cycles 2 CYC64 64 clock cycles 3 CYC128 128 clock cycles 4 CYC256 256 clock cycles 5 CYC512 512 clock cycles 6 CYC1024 1024 clock cycles 7 CYC2048 2048 clock cycles 8 CYC4096 4096 clock cycles 9 INTENCLR Interrupt Enable Clear 0x4 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTENSET Interrupt Enable Set 0x5 8 read-write n 0x0 0x0 EW Early Warning Interrupt Enable 0 1 INTFLAG Interrupt Flag Status and Clear 0x6 8 read-write n 0x0 0x0 EW Early Warning 0 1 SYNCBUSY Synchronization Busy 0x8 32 read-only n 0x0 0x0 ALWAYSON Always-On Synchronization Busy 3 1 CLEAR Clear Synchronization Busy 4 1 ENABLE Enable Synchronization Busy 1 1 WEN Window Enable Synchronization Busy 2 1